Big Changes In Patterning

The shift to GPU-accelerated mask writing and curvilinear shapes could fundamentally change chip design and manufacturing.


Aki Fujimura, CEO of D2S, sat down with Semiconductor Engineering to discuss patterning issues at 10nm and below, including mask alignment, the need for GPU acceleration, EUV’s future impact on the total number of masks, and what the re-introduction of curvilinear shapes will mean for design.

SE: Patterning issues are getting a lot of attention at 10nm and 7nm. When do they really start showing up?

Fujimura: We’re running into them already. The world has been ready to transition to EUV for a long time. What’s amazing is that even without EUV becoming production-ready, the industry has been able to continue pushing , using multi-patterning as well as computational lithography. There is more and more complex OPC (optical proximity correction), which creates more and more complex shapes on the mask in order to increase process margin on the wafer.

SE: So what happens next?

Fujimura: EUV might not be ready exactly at the node predicted, but we still need to get the infrastructure ready for the next generation. That includes EUV, which is the most anticipated. The world hopes that EUV comes along very quickly. But if it doesn’t, there are other technologies, such as nanoimprint and directed self-assembly (DSA), or e-beam direct write doing complementary lithography. All of these possibilities are being explored, and some are nearing production level. But if EUV comes along, the world probably will settle on that.

SE: There are a couple of metal layers that are the most problematic—metal 1 and metal 2. As shrinking continues, does that start affecting the other layers, too?

Fujimura: Yes. The transistor level is the most critical layer. In lithography, the most difficult to print are the contacts and vias. Those are the first to suffer when you go to smaller nodes. All of the via levels are difficult, and in the lower layers it’s particularly difficult. Even cut layers, which are small features but a little easier than vias and contacts, are becoming difficult.

SE: What’s the path forward, including if EUV doesn’t become a viable solution?

Fujimura: EUV probably will happen. But the biggest thing I’m seeing is the Toshiba-Hynix collaboration on nanoimprint for memory devices, specifically flash. That seems to be on a good track. It seems like memory has the right focus with anything that has a defectivity issue because memory designs already are redundant. They can withstand a few known failures. It’s very difficult for logic to use nanoimprint.

SE: Where are we on edge alignment?

Fujimura: 7nm will be okay if EUV is ready, but even with EUV multiple patterning will be necessary eventually. Alignment is a big issue with multiple patterning. The industry’s trick was to make critical dimension size of the feature the only important thing. You could be a little bit off on placement and spacing and it was okay, as long as the lines themselves were the right size. That’s no longer true. You’re overlaying on top of each other, so even lines themselves are formed by spaces. It becomes much more important to make the exact edge placement correct. When the semiconductor industry needs something, it figures out a solution. Nobody is predicting doom and gloom because of that issue. It will be difficult, but we just need to pay attention to it and do a good job.

SE: Where is inverse lithography, and how does that fit in here?

Fujimura: Inverse lithography has become critical. Everyone is predicting that, even with EUV, there is a need for at least OPC. And some people, including me, believe other technologies that have been developed will be required. Once inverse technology is in production use, why not take advantage of that to get extra process margin in EUV because you always need it. If you step back and look at this market, there are three discontinuities in the market. The best known is EUV. The other two are the emergence of multi-beam mask writing and GPU acceleration, which enables curvilinear shapes.

SE: What changes with curvilinear shapes?

Fujimura: Mask shapes have been written using variable shaped beams for the last 20 years. Those have shaped apertures. You can only print accurately things that are rectilinear, or sometimes 45 degree angles. That limitation came about because 20 years ago inventors figured out that mask shapes almost always seemed to be Manhattan rectilinear. That has become the standard. But before that happened, because of CAD limitations, design shapes were almost always rectilinear. There were occasional inductors that were circles, but 99.99% of features on any mask that you saw 20 years ago were orthogonal rectilinear. We call it Manhattan because it looks like a rectilinear grid. The Manhattan features were taken advantage of for data representation and things like that. On the CAD side, there is a lot of acceleration that’s possible for geometric computation algorithms where features are rectangular. Most computation of geometry breaks things down into constituent rectangles and handles them that way. When VSB (variable shape beam) technology became the norm, it became necessary to have designs be orthogonal and rectilinear. That’s all you could write on a mask.

SE: Where do we go next?

Fujimura: Multi-beam is coming around, and in multi-beam the constituent writing unit is a 20nm x 20nm or 10nm x 10nm pixel. This is 5nm x 5nm or 2.5nm x 2.5nm on the wafer dimension. Because of that, you can write any curvilinear shape you want on a mask. This is ideal for GPUs, because a GPU is extremely good at handling pixel kinds of data. So the CAD side can now become curvilinear. It doesn’t need to adhere to the Manhattan limitations.

SE: What does that buy you in design?

Fujimura: Two things. First, in trying to save power, shorter distance is always better. You can now achieve that. But even more important will be the design-to-manufacturing link. Trying to make things more manufacturable, particularly when you’re adding a Manhattan jog, is very difficult to do. When you do a small jog in one layer, that’s usually considered a bad thing. When you try to manufacture that it won’t come out anything like a small jog. It will come out like a little curved feature. Being able to print a Manhattan jog was impossible, so you had to take special steps to be able to handle that. Now you can design things in the way that the manufacturing side can actually manufacture them. This allows a reliably manufacturable design.

SE: What has to change on the manufacturing side?

Fujimura: Nothing. The whole idea is to take what manufacturing can do as a given, and then design to it. The key enabling factor is to be able to handle curvilinear designs. The key technologies need to do that are multi-beam mask writing, so the mask writers can write curvilinear features, and GPU acceleration, so that computing can happen in a reasonable amount of time.

SE: How much of this goes the other way, so that if it can be manufactured you can have more freedom in your design?

Fujimura: Underlying this is an inherent need on the design side to be more creative than the Manhattan assumptions allowed. For 20 years, it had to be Manhattan. Removing those constraints will unleash human ingenuity to take advantage of this capability. It will take time, though.

SE: Do the new memory types benefit from this?

Fujimura: All of the memory types can benefit. I’m a proponent of the reliable manufacturing methodology for any memory design. Allowing curvilinear design is just one example. All of those memories can benefit on the physical design side, though, if they aren’t restricted to Manhattan shapes.

SE: How is this message being disseminated?

Fujimura: For the first time, PMJ (Photomask Japan) is featuring a keynote speaker by Nvidia, followed by two sessions on GPU acceleration. It’s going to have a different look to the conference. But there are many different things that already are taking place. SEM (scanning electron microscope) inspection of masks takes a picture of masks and then does a little simulation and allows the customer to see a wafer-area image out of a mask picture. This is GPU accelerated.

SE: Is the goal to speed up the mask process, or to allow you to do more within the same amount of time?

Fujimura: Both. Being able to do the wafer plane analysis like that is a big advantage. SEM images are always curvilinear. It’s not the CAD shape that you draw that goes into it. It’s what comes out of that, which is curvilinear. In the past, that has been very slow because it was based on CPUs. But with GPU acceleration, it’s very fast. You can see a picture of the mask and what it would look like in wafer production at the same time.

SE: That’s a huge step forward, right?

Fujimura: Yes, and it’s not just accelerating what was done. You have new capabilities. If you’re trying to look at the disposition of a defect—does this piece of dust on the mask matter on the wafer, and does the wafer production even see the dust—that’s a new capability. From a processing standpoint, you don’t have to do it on a separate machine. You can just do that when you’re taking a SEM picture. It speeds up the process.

SE: Where else is GPU acceleration being used?

Fujimura: The NuFlare EBM-9500, which is writing most leading-edge masks today, has a GPU-accelerated mechanism in it. It’s simulating the temperature of every part of the mask as you write these shots. And it adjusts the dose of the VSB shots as it writes by predicting the temperature on the surface rather than measuring it, which is difficult to do. It predicts by simulation what the temperature will be. This is necessary because the machine has 1,200 A/cm². It’s a very strong, sustained current so it heats up the mask.

SE: What does the temperature do to the mask, particularly if it’s too hot?

Fujimura: It’s a resist-coated mask. If the temperature is higher, it gets exposed a little quicker, so the mask critical dimension is going to grow a little bit. That could be 2nm or 4nm, which is too much for the mask world. Every EBM-9500 today uses GPU acceleration. It’s about 350 teraflops of GPU acceleration.

SE: So you’re providing the instant feedback that shows if you do something ‘this way,’ here’s the effect?

Fujimura: Yes, and it requires close collaboration so it’s harder. But that’s what the industry is evolving to. You need to be able to work together to achieve these kinds of things. This relationship that D2S has with NuFlare is extending to the next step for NuFlare’s multi-beam machine, the MBM-1000. We also are providing the software that will be doing some multi-beam correction.

SE: Drilling down, what is the impact of GPU acceleration?

Fujimura: The only way that multi-beam machines can have the kind of mask correction that it needs is if you use GPU acceleration to solve that. Multi-beam shoots 512 x 512 (262,144) pixels at the same time. Being able to process that in real time is very difficult without the power of GPUs.

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