tag: PAM-4

A Flip-Chip, Co-Packaged With Photodiode, High-speed TIA in 16nm FinFET CMOS
By Technical Paper Link - 20 Jul, 2023 - Comments: 0

A technical paper titled "A 112-Gb/s —8.2-dBm Sensitivity 4-PAM Linear TIA in 16-nm CMOS With Co-Packaged Photodiodes" was published by researchers at University of Toronto, Alphawave IP, and Huawei Technologies Canada. Abstract: "A flip-chip co-packaged linear transimpedance amplifier (TIA) in 16-nm fin field effect transistor (FinFET) CMOS demonstrating 112-Gb/s four-level pulse-amplitude... » read more

A Sea Change In Signaling With PCIe 6.0
By Tim Messegee - 12 May, 2022 - Comments: 0

PCI Express (PCIe) is one of those standards from the PC world, like Ethernet, that has proliferated far beyond its original application space. Thanks to its utility and economies of scale, PCIe has found a place in applications in IoT, automotive, test and measurement, medical, and more. As it has scaled, PCIe has pushed NRZ signaling to higher and higher levels reaching 32 gigatransfers per s... » read more

The Ethernet Standard: To IP And Beyond
By Jerry Lotto - 13 Jan, 2022 - Comments: 0

Ethernet is ubiquitous—it is the core technology that defines the Internet and serves to connect the world in ways that people could not imagine even one generation ago. HPC clusters are working on solving the most challenging problems facing humanity—and cloud computing is the service hosting many of the application workloads struggling with these questions. While alternative network infra... » read more

More Errors, More Correction in Memories
By Bryon Moyer - 09 Nov, 2021 - Comments: 1

As memory bit cells of any type become smaller, bit error rates increase due to lower margins and process variation. This can be dealt with using error correction to account for and correct bit errors, but as more sophisticated error-correction codes (ECC) are used, it requires more silicon area, which in turn drives up the cost. Given this trend, the looming question is whether the cost of ... » read more

Retimers Replacing Redrivers As Signal Speeds Increase
By Bryon Moyer - 08 Jul, 2021 - Comments: 1

Retimers are undergoing a renaissance as new PHY protocols prove too demanding for redrivers. Redrivers and retimers both have been used to extend wired signal reach over the years. But redrivers have dominated this space due to their relative simplicity and lower cost. That balance is beginning to change. “A retimer represents three things no one wants in their system — area, cost, a... » read more

Getting Ready For An Efficient Shift To PCI Express 6.0 Designs With Optimized IP
By Gary Ruggles - 10 Jun, 2021 - Comments: 0

PCI Express (PCIe) 6.0 technology with key changes will bring about challenges that high-performance computing, artificial intelligence, and storage system-on-chip (SoC) designers will face. This article provides designers a summary of the major changes and how they can be handled to ensure a smooth and successful transition to PCIe 6.0. The three major changes in PCIe 6.0 that designers nee... » read more

What’s After PAM-4?
By Bryon Moyer - 23 Jun, 2020 - Comments: 1

[This is part 2 of a 2-part series. Part 1 can be found here.] The future of high-speed physical signaling is uncertain. While PAM-4 remains one of the key standards today, there is widespread debate about whether PAM-8 will succeed it. This has an impact on everything from where the next bottlenecks are likely to emerge and the best approaches to solving them, to how chips, systems and p... » read more

High-Speed Signaling Drill-Down
By Bryon Moyer - 17 Jun, 2020 - Comments: 0

Chip interconnect standards have received a lot of attention lately, with parallel versions proliferating for chiplets and serial versions moving to higher speeds. The lowliest characteristic of these interconnect schemes is the physical signaling format. Having been static at NRZ (non-return-to-zero) for decades, change is underway. “Multiple approaches are likely to emerge,” said Brig ... » read more

Die-To-Die Connectivity
By Ed Sperling - 22 Nov, 2019 - Comments: 0

Manmeet Walia, senior product marketing manager at Synopsys, talks with Semiconductor Engineering about how die-to-die communication is changing as Moore’s Law slows down, new use cases such as high-performance computing, AI SoCs, optical modules, and where the tradeoffs are for different applications.   Interested in more Semiconductor Engineering videos? Sign-up for our YouTu... » read more

Virtual Packages Improve Signal Integrity
By Jeff McGuire - 23 Oct, 2018 - Comments: 0

The 112 Gb/s generation of SerDes has brought along excessive loss within the package, around 5 dBs of loss within each monolithic package. This loss markedly reduces the usefulness of these SerDes. MCM technology has progressed to where the use of 70mm packages is routine. Non-interposer MCMs easily can use 20 or more chiplets, plus large dies and passives can be used. These MCMs have low ... » read more

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