Do Parallel Tools Make Sense?


Semiconductor Engineering sat down to talk about parallelization efforts within EDA with Andrea Casotto, chief scientist for Altair; Adam Sherer, product management group director in the System & Verification Group of Cadence; Harry Foster, chief scientist for Mentor, a Siemens Business; Vladislav Palfy, global manager for applications engineering at OneSpin; Vigyan Singhal, chief Oski for ... » read more

Your Job is Harder Than Mine


What I do for a living is listen – a lot – and try to make sense of the myriad challenges that I hear about in terms of design and managing power and performance. What you do as an architect, design engineer or verification engineer is live in the trenches with it all, every day. I admire and respect that. This is especially true as I recently pondered and talked with industry luminaries... » read more

Keeping The Balance


By Ann Steffora Mutschler The brains of datacenters today are more powerful than ever due to technology advancements in chip architectures and in manufacturing processes that allow more processing power thanks to Moore’s Law. But knowing exactly how and where to configure the processors and cores for optimum throughput and performance within a certain power budget raises a number of qu... » read more