Using A System Technology Co-Optimization (STCO) Approach For 2.5/3D Heterogeneous Semiconductor Integration

By Siemens EDA - 23 Jun, 2021 - Comments: 0

With the economics of transistor scaling no longer universally applicable, the industry is turning to innovative packaging technologies to support system scaling demands and achieve lower system cost. This has led to the system technology co-optimization (STCO) concept, where a SoC type system is disaggregated, or partitioned, into smaller modules (also known as chiplets) that can be asynchrono... » read more

Shifting Auto Architectures

By Ed Sperling - 29 Apr, 2021 - Comments: 0

Domain controllers and gateways are being replaced by central processing modules and zonal gateways to handle all of the data traffic in a vehicle. Ron DiGiuseppe, automotive IP segment manager at Synopsys, talks with Semiconductor Engineering about how automotive applications are changing, what that means for engineering teams, and how they will shift as AI is increasingly deployed. » read more

Design Issues For Chips Over Longer Lifetimes

By Ed Sperling - 08 Mar, 2021 - Comments: 0

Semiconductor Engineering sat down to discuss the myriad challenges associated with chips used in complex systems over longer periods of time them with Jean-Marie Brunet, senior director for the Emulation Division at Siemens EDA; Frank Schirrmeister, senior group director for solution marketing at Cadence; Maurizio Griva, R&D Manager at Reply; and Laurent Maillet-Contoz, system and architec... » read more

Is Hardware-Assisted Verification Avoidable?

By Brian Bailey - 29 Oct, 2020 - Comments: 1

Emulation is emerging as the tool of choice for complex and large designs, but companies that swap from simulation to emulation increasingly recognize this is not an easy transition. It requires money, time, and effort, and even then not everyone gets it right. Still, there are significant benefits to moving from simulation to emulation, providing these systems can be utilized efficiently en... » read more

Challenges At 3/2nm

By Ed Sperling - 15 Sep, 2020 - Comments: 0

David Fried, vice president of computational products at Lam Research, talks about issues at upcoming process nodes, the move to EUV lithography and nanosheet transistors, and how process variation can affect yield and device performance. » read more

Making Everything Linux-Capable

By Ed Sperling - 04 Sep, 2020 - Comments: 0

It's not clear how the edge will play out or what will be the winning formula from a hardware standpoint. But for everything beyond the end device, and possibly even including the end device, a key prerequisite will be the ability to run Linux. That means at least one processor or core within the hardware will need to run 64-bit software. In addition, systems will need to have enough storage... » read more

Getting Particular About Partitioning

By Ed Sperling - 31 Aug, 2020 - Comments: 0

Partitioning could well be one of the most important and pervasive trends since the invention of computers. It has been around for almost as long, too. The idea dates back at least as far back as the Manhattan Project during World War II, when computations were wrapped within computations. It continued from there with what we know as time-sharing, which rather crudely partitioned access by p... » read more

New Architectures, Much Faster Chips

By Ed Sperling and Ann Mutschler - 31 Aug, 2020 - Comments: 0

The chip industry is making progress in multiple physical dimensions and with multiple architectural approaches, setting the stage for huge performance increases based on more modular and heterogeneous designs, new advanced packaging options, and continued scaling of digital logic for at least a couple more process nodes. A number of these changes have been discussed in recent conferences. I... » read more

FPGA Prototyping Complexity Rising

By Ann Mutschler - 28 May, 2020 - Comments: 0

Multi-FPGA prototyping of ASIC and SoC designs allows verification teams to achieve the highest clock rates among emulation techniques, but setting up the design for prototyping is complicated and challenging. This is where machine learning and other new approaches are beginning to help. The underlying problem is that designs are becoming so large and complex that they have to be partitioned... » read more

Re-Imagining The GPU

By Susan Rambo And Ed Sperling - 23 Apr, 2020 - Comments: 0

John Rayfield, CTO at Imagination Technologies, sat down with Semiconductor Engineering to talk about RISC-V, AI, and computing architectures. What follows are excerpts of that conversation. SE: What your plans are for RISC-V? Rayfield: We're actively finalizing the integration of RISC-V cores into future-generation GPUs. That work has been going on for several months. Moving forward, we'... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: partitioning