tag: patterning

Defect Challenges Grow At The Wafer Edge
By Laura Peters - 10 Sep, 2024 - Comments: 0

Reducing defects on the wafer edge, bevel, and backside is becoming essential as the complexity of developing leading-edge chips continue to increase, and where a single flaw can have costly repercussions that span multiple processes and multi-chip packages. This is made more difficult by the widespread rollout of such processes as hybrid bonding, which require pristine surfaces, and the gro... » read more

Key Technologies To Extend EUV To 14 Angstroms
By Laura Peters - 29 Jul, 2024 - Comments: 2

The top three foundries plan to implement high-NA EUV lithography as early as 2025 for the 18 angstrom generation, but the replacement of single exposure high-NA (0.55) over double patterning with standard EUV (NA = 0.33) depends on whether it provides better results at a reasonable cost per wafer. So far, 2024 has been a banner year for high-numerical aperture EUV lithography. Intel Foundry... » read more

Precision Patterning Options Emerge For Advanced Packaging
By Gregory Haley - 23 Jul, 2024 - Comments: 0

The chip industry is ratcheting up investments in advanced packaging as it strives to keep pace with demands for increased functionality and higher performance, including novel patterning technologies that can reduce costs and speed time to market. Success in advanced packages is partly dependent on effectively managing the interconnectivity between the chips, which requires increasingly pre... » read more

Exploring The Fundamentals Of Photolithography
By Joyce Lowes - 23 May, 2024 - Comments: 0

In the semiconductor materials industry, photolithography is a crucial technology for creating intricate electronic circuits. Essentially, it’s the art of printing at the nanoscale level, enabling the precise patterning of semiconductor materials. The ability to do this well is important for companies in the industry because it determines how detailed and efficient microchips can be. This aff... » read more

Semiconductor Device Manufacturing Process Challenges And Opportunities
By Andreas Bier - 07 Dec, 2023 - Comments: 0

Semiconductor device manufacturing involves a complex series of processes that transform raw materials into finished devices. The process typically involves four major stages: wafer fabrication, wafer testing, assembly or packaging, and final testing. Each stage has its own unique set of challenges and opportunities. The semiconductor device manufacturing process faces several challenges, inclu... » read more

Novel Assist Layers To Enhance EUV Lithography Performance Of Photoresists On Different Substrates
By Brewer Science - 16 Aug, 2023 - Comments: 0

In EUV lithography, good resist patterning requires an assist layer beneath it to provide adhesion to prevent pattern collapse of small features and allow for higher aspect ratios. In addition, future EUV high numerical aperture (NA) is expected to require a decrease in thickness from the overall patterning stack. In this study, we are exploring a fundamentally new approach to developing an alt... » read more

Direct Synthesis of Planar (2D) Micro and Nanopatterned Epitaxial Graphene on SiC
By Technical Paper Link - 28 Jul, 2023 - Comments: 0

A technical paper titled “Direct synthesis of nanopatterned epitaxial graphene on silicon carbide” was published by researchers at University of Technology Sydney, Ludwig-Maxilimians Universität München, Monash University, and Imperial College London. Abstract: "This article introduces a straightforward approach for the direct synthesis of transfer-free, nanopatterned epitaxial graphene... » read more

Nanoimprint Finally Finds Its Footing
By Gregory Haley - 20 Apr, 2023 - Comments: 2

Nanoimprint lithography, which for decades has trailed behind traditional optical lithography, is emerging as the technology of choice for the rapidly growing photonics and biotech chips markets. First introduced in the mid-1990s, nanoimprint lithography (NIL) has consistently been touted as a lower-cost alternative to traditional optical lithography. Even today, NIL potentially is capable o... » read more

Insights Into Advanced DRAM Capacitor Patterning: Process Window Evaluation Using Virtual Fabrication
By Qingpeng Wang - 20 Oct, 2022 - Comments: 0

With continuous device scaling, process windows have become narrower and narrower due to smaller feature sizes and greater process step variability [1]. A key task during the R&D stage of semiconductor development is to choose a good integration scheme with a relatively large process window. When wafer test data is limited, evaluating the process window for different integration schemes can... » read more

Pathfinding By Process Window Modeling
By Coventor - 19 Oct, 2022 - Comments: 0

In advanced DRAM, capacitors with closely packed patterning are designed to increase cell density. Thus, advanced patterning schemes, such as multiple litho-etch, SADP and SAQP processes may be needed. In this paper, we systematically evaluate a DRAM capacitor hole formation process that includes SADP and SAQP patterning, using virtual fabrication and statistical analysis in SEMulator3D®. The ... » read more

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