PCIe IP With Enhanced Security For The Automotive Market

By Dana Neustadter - 07 Nov, 2024 - Comments: 0

The automotive industry is undergoing a rapid transformation, with connectivity and automation becoming integral components of modern vehicles. However, this increased connectivity also brings heightened risks. The automotive industry takes many measures to ensure safety for vehicles, but it is crucial to understand that these safety measures are ineffective if the vehicle's security is comprom... » read more

Formally Modeling and Verifying CXL Cache Coherence (Imperial College London)

By Technical Paper Link - 22 Oct, 2024 - Comments: 0

A new technical paper titled "Formalising CXL Cache Coherence" was published by researchers at Imperial College London. Abstract "We report our experience formally modelling and verifying CXL.cache, the inter-device cache coherence protocol of the Compute Express Link standard. We have used the Isabelle proof assistant to create a formal model for CXL.cache based on the prose English spec... » read more

PIO on Current HW Outperforms DMA Over a Range of Payload Sizes In A Number of Different Applications (ETH Zurich)

By Technical Paper Link - 11 Oct, 2024 - Comments: 0

A new technical paper titled "Rethinking Programmed I/O for Fast Devices, Cheap Cores, and Coherent Interconnects" was published by researchers at ETH Zurich. Abstract: "Conventional wisdom holds that an efficient interface between an OS running on a CPU and a high-bandwidth I/O device should be based on Direct Memory Access (DMA), descriptor rings, and interrupts: DMA offloads transfers fr... » read more

Partial Header Encryption In Integrity And Data Encryption For PCIe

By Kunal Chhabriya - 10 Oct, 2024 - Comments: 0

Partial Header Encryption (PHE) is an additional mechanism added to Integrity and Data Encryption (IDE) in PCIe 6.0 to prevent side-channel attacks based on attacker analysis of the information included in the headers. This blog narrates PHE flow and Cadence VIP support for PHE in IDE across PCIe/CXL protocols. Background Introducing PCIe's Integrity and Data Encryption Feature is an excell... » read more

CMA/SPDM—An Additional Layer of Security for PCIe Transport

By Suprio Biswas - 10 Oct, 2024 - Comments: 0

In today’s data-driven world, everyone is navigating a vast ocean of information that transcends across unsecured links and can easily fall prey to digital hackers. To keep our data safe, it is crucial to beef up security and make sure that only the right users can access our data. This article dives into the world of secure communication, where component measurement and authentication (CM... » read more

PCIe Over Optical: Transforming High-Speed Data Transmission

By David Kulansky - 29 Aug, 2024 - Comments: 0

With the rise in AI requiring new computing models and enhanced data transmission methods to cope, the necessity for innovative, high-performance, and low-latency connectivity solutions has never been more apparent. PCIe over Optical is set to play a key role in enabling the growth of AI, and here we examine some of the intricacies of PCIe over Optical to explore its implementation, challenges,... » read more

Unifying Storage Diversity: Leveraging PCIe IP for Multi-Device, Multi Form Factor Designs

By Synopsys - 24 Jul, 2024 - Comments: 0

In the fast-paced world of data storage, designers are racing to keep up with ever-evolving interface standards and form factors. This whitepaper explores the impact of these industry shifts, focusing on the integration of PCIe interfaces within the context of varying storage device form factors like the Enterprise and Datacenter Standard Form Factor (EDSFF). PCIe designs need to be flexible in... » read more

Essential Insights for Design PCIe 6.0 Interconnects

By Keysight - 24 Jul, 2024 - Comments: 0

PCI Express (PCIe) is a serial communication protocol that has progressed through generations to enhance data rates and functionality. The latest version, PCIe 6.0, doubles the data rate to 64 GT/s, enabling up to 256 GB/s of bandwidth in an x16 configuration. The technology incorporates PAM4 signaling and forward error correction to maintain high speeds with improved signal integrity and relia... » read more

Survey of CXL Implementations and Standards (Intel, Microsoft)

By Technical Paper Link - 22 Jul, 2024 - Comments: 0

A new technical paper titled "An Introduction to the Compute Express Link (CXL) Interconnect" was published by researchers at Intel Corporation, Microsoft, and University of Washington. Abstract "The Compute Express Link (CXL) is an open industry-standard interconnect between processors and devices such as accelerators, memory buffers, smart network interfaces, persistent memory, and solid-... » read more

PCIe 7.0: Speed, Flexibility & Efficiency For The AI Era

By Lou Ternullo - 18 Jul, 2024 - Comments: 0

As the industry came together for PCI-SIG DevCon last month, one thing took center stage, and that was PCI Express 7.0. While still in the final stages of development, the world is certainly ready for this significant new milestone of the PCIe specification. Let’s look at how PCIe 7.0 is poised to address the escalating demands of AI, high-performance computing, and emerging data-intensive ap... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

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by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?