Top 15 Integrating Points In The Continuum Of Verification Engines

By Frank Schirrmeister - 30 Jul, 2015 - Comments: 0

The integration game between the different verification engines, dynamic and static, is in full swing. Jim Hogan talked about the dynamic engines that he dubbed “COVE”, and I recently pointed out a very specific adoption of COVE in my review of some customer examples at DAC 2015 in “Use Model Versatility Is Key for Emulation Returns on Investment”. Here are my top 15 integrating poin... » read more

One PHY Does Not Fit All

By Rita Horner - 14 May, 2015 - Comments: 0

Consumers expect their battery-operated mobile devices to be faster, smaller and more reliable while providing greater functionality at a reduced cost. Most of all, consumers demand longer battery life and 24/7 access to data. To meet these demands, consumer system-on-a-chip (SoC) designers must make tradeoffs between features, performance, power and cost. Enterprise SoC designers have their... » read more

Blog Review: April 15

By Jesse Allen - 15 Apr, 2015 - Comments: 0

How much memory do you need to look 13 billion years in the past? Rambus' Aharon Etengoff ponders the Square Kilometre Array's massive number of radio telescopes and what it means for computing. NXP's Martin Schoessler argues that for smart cities to work for their citizens, both technology companies and government entities will need a new mind-set. Reinventing the wheel is a good thing i... » read more

The Week In Review: Design/IoT

By Ed Sperling - 12 Dec, 2014 - Comments: 0

Tools Cadence rolled out a use-case scenario verification tool that automates some test development that has been done manually in the past. The new tool accelerates development of software-driven tests and debug to ferret out complex SoC-level bugs. Cadence claims a 10X productivity improvement. Mentor Graphics uncorked a new version of its verification IP for PCI Express. The new IP decre... » read more

Optimizing Analog For Power At Advanced Nodes

By Ann Mutschler - 09 Oct, 2014 - Comments: 0

As any engineering manager will tell you, analog and digital engineers seem like they could be from different planets. While this has changed somewhat over time, [getkc id="52" comment="analog"] is still something of a mystery to many in [getkc id="81" kc_name="SoC"] design teams. Throw power management into the mix and things really get interesting. Improvements in analog/mixed-signal tools... » read more

Using PCI Express L1 Sub-states To Minimize Power Consumption In Advanced Process Nodes

By Rita Horner - 10 Jul, 2014 - Comments: 0

The major sources of Internet traffic are shifting from wired to wireless and mobile devices. With the growing regulatory requirements and increased consumer pressure for more power-efficient products, designers need to better understand and optimize the power consumption of battery-operated devices. Power consumption of a portable device widely varies based on the user’s behavior and appl... » read more

Blog Review: July 2

By Ed Sperling - 02 Jul, 2014 - Comments: 0

Mentor’s Nazita Saye has reservations about driverless cars. Sometimes it’s actually fun to drive—and sometimes it isn’t. Cadence’s Brian Fuller is a bit more optimistic about driverless cars. He says that from the standpoint of safety, efficiency and environment, autonomous vehicles will be a big step forward—if and when some critical problems are solved. And along the same... » read more

Blog Review: April 2

By Ed Sperling - 02 Apr, 2014 - Comments: 0

Mentor’s Nazita Saye compares roadway roundabouts to networked systems. One roundabout works fine, but add in a bunch of them and you have a massive traffic jam. How many roundabouts are in your design? Cadence’s Richard Goering interviews Stan Kroliskoski, chair of the IEEE Design Automation Standards Committee, about four working groups on EDA standards and what’s ahead. Speaking ... » read more

Advanced Verification IP Accelerates PCIe Integration Test

By Various Writers - 10 Oct, 2013 - Comments: 0

System-on-chip (SoC) complexity is being driven by platform convergence and the need for more processing power and lower power consumption. The complexity of SoC standards-based interfaces has similarly increased for the same reasons: low power, improved quality of service and high throughput. Design teams have adopted IP and reuse for designs of these complex protocols so they can focus their ... » read more

The Week In Review: Aug 5

By Ed Sperling - 05 Aug, 2013 - Comments: 0

By Mark LaPedus According to a nationwide online survey conducted by Harris Interactive on behalf of Crucial.com, 36% of those Americans who experienced PC problems in the past six months admit they have lashed out at their slow, underperforming computers by using profanity, screaming and shouting, or by striking it with a fist or other object. Those who experienced computer problems also indi... » read more

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tag: PCIe