tag: PCIe

Advanced Verification IP Accelerates PCIe Integration Test
By Various Writers - 10 Oct, 2013 - Comments: 0

System-on-chip (SoC) complexity is being driven by platform convergence and the need for more processing power and lower power consumption. The complexity of SoC standards-based interfaces has similarly increased for the same reasons: low power, improved quality of service and high throughput. Design teams have adopted IP and reuse for designs of these complex protocols so they can focus their ... » read more

The Week In Review: Aug 5
By Ed Sperling - 05 Aug, 2013 - Comments: 0

By Mark LaPedus According to a nationwide online survey conducted by Harris Interactive on behalf of Crucial.com, 36% of those Americans who experienced PC problems in the past six months admit they have lashed out at their slow, underperforming computers by using profanity, screaming and shouting, or by striking it with a fist or other object. Those who experienced computer problems also indi... » read more

Pitfalls In Subsystem Reuse
By Ann Mutschler - 30 May, 2013 - Comments: 0

By Ann Steffora Mutschler IP subsystems provide a ‘divide and conquer’ approach to SoC design by combining multiple IP blocks together to perform individual functions such as audio, graphics or video. The advantage of this approach is that these functions can be tested and verified at the unit level then integrated with the top-level SoC. This also facilitates reuse because each of ... » read more

Taking Aim At Big Data
By Ed Sperling - 25 Apr, 2013 - Comments: 0

By Ed Sperling As the Internet of Things bridges the gap between the mobile and big data worlds, EDA and IP vendors increasingly are looking well beyond their usual boundaries. How successful they are at moving upward into a market that is far less price-sensitive remains to be seen. But from a technology standpoint, at least, the issues encountered by data centers and cloud providers are ... » read more

High Speed PCB Layout: Physical Design Issues Of Highspeed Interfaces
By Various Writers - 28 Jun, 2012 - Comments: 0

Moore’s law, applied to data rates, has pushed PCB circuits so fast that the layout becomes part of the circuit. In designs such as DDR3 and PCIe, the fastest memory and high-speed serial performance comes with very specific physical layout requirements that are not obvious. Unless you are thinking like an RF designer, there are many unexpected challenges to a successful high-speed layout. A ... » read more

Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy