Pitfalls In Subsystem Reuse

By Ann Mutschler - 30 May, 2013 - Comments: 0

By Ann Steffora Mutschler IP subsystems provide a ‘divide and conquer’ approach to SoC design by combining multiple IP blocks together to perform individual functions such as audio, graphics or video. The advantage of this approach is that these functions can be tested and verified at the unit level then integrated with the top-level SoC. This also facilitates reuse because each of ... » read more

Taking Aim At Big Data

By Ed Sperling - 25 Apr, 2013 - Comments: 0

By Ed Sperling As the Internet of Things bridges the gap between the mobile and big data worlds, EDA and IP vendors increasingly are looking well beyond their usual boundaries. How successful they are at moving upward into a market that is far less price-sensitive remains to be seen. But from a technology standpoint, at least, the issues encountered by data centers and cloud providers are ... » read more

High Speed PCB Layout: Physical Design Issues Of Highspeed Interfaces

By Various Writers - 28 Jun, 2012 - Comments: 0

Moore’s law, applied to data rates, has pushed PCB circuits so fast that the layout becomes part of the circuit. In designs such as DDR3 and PCIe, the fastest memory and high-speed serial performance comes with very specific physical layout requirements that are not obvious. Unless you are thinking like an RF designer, there are many unexpected challenges to a successful high-speed layout. A ... » read more

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Knowledge Centers
Entities, people and technologies explored

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tag: PCIe

Pitfalls In Subsystem Reuse

Taking Aim At Big Data

High Speed PCB Layout: Physical Design Issues Of Highspeed Interfaces