The Week In Review: Design/IoT

Cadence rolls out use-case scenario verification tool; Mentor adds PCIe VIP; Synopsys updates place-and-route tool, adds LPDDR4 VIP; Coverity looks at defect density; ANSYS-Apache wins deal with Solarflare.


Cadence rolled out a use-case scenario verification tool that automates some test development that has been done manually in the past. The new tool accelerates development of software-driven tests and debug to ferret out complex SoC-level bugs. Cadence claims a 10X productivity improvement.

Mentor Graphics uncorked a new version of its verification IP for PCI Express. The new IP decreases testbench assembly time and FPGA design verification by up to 10X, according to Mentor.

Synopsys announced the latest release of its place-and-route tool, adding multi-objective concurrent clock and data optimization, early support 10nm processes, and a 10X productivity gain.  The company also introduced LPDDR4 verification IP that includes verification plans, built-in coverage and a protocol-aware debug environment. The VIP is 100% based on SystemVerilog UVM. Synopsys also rolled out a new version of its illumination design tool that takes into account glare in a room and support for backlit designs.

Coverity issued its latest scan report on defect density for open source software, showing decreases over last year. The company, a division of Synopsys, analyzed Apache Hadoop, HBase and Cassandra.

ANSYS-Apache won a deal with Solarflare, which will use its power and reliability signoff tools for application-intelligent 10/40 Gbit Ethernet products.

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