Productivity Keeping Pace With Complexity

By Brian Bailey - 24 Sep, 2020 - Comments: 0

Designs have become larger and more complex and yet design time has shortened, but team sizes remain essentially flat. Does this show that productivity is keeping pace with complexity for everyone? The answer appears to be yes, at least for now, for a multitude of reasons. More design and IP reuse is using more and larger IP blocks and subsystems. In addition, the tools are improving, and mo... » read more

PCIe 5.0: A Key Interface Solution For The Evolving Data Center

By Vinitha Seevaratnam - 10 Sep, 2020 - Comments: 0

A great many developments are shaping the evolution of the data center. Enterprise workloads are increasingly shifting to the cloud, whether these be hosted or colocation implementations. The nature of workload traffic is changing such that data centers are architected to manage greater east-west (within the data center) communication. New workloads, with AI/ML (artificial intelligence/machine ... » read more

Accelerating Simulation Of PCIe Controllers For DMA Applications

By Akshay Sarup - 10 Sep, 2020 - Comments: 0

For memory-intensive and high-performance computing, direct memory access (DMA) is indispensable. A typical DMA operation in PCI Express (PCIe) entails the transfer of data from the system memory to end point devices using a point-to-point PCIe bus to reduce latency and increase memory access throughput between the CPU and the device. Verification of DMA engines is concentrated on the data t... » read more

Astera Labs: Purpose-Built Connectivity

By Ed Sperling - 14 Aug, 2020 - Comments: 0

Growing amounts of data are forcing companies to rethink where data is processed and when, how and where it is moved. But solutions may vary greatly from one company to the next, and from one use case or application to the next. This is forcing the adoption of a heterogenous compute architecture that combines traditional processors, such as CPUs, GPUs and FPGAs, with AI processors and smart net... » read more

How UVM Callbacks Simplify Assertion Validation

By Akshay Sarup - 13 Aug, 2020 - Comments: 0

By Akshay Sarup and Mark Olen Assertions bring immediate benefits to the whole design and verification cycle; thus any challenges engineers face in coding and testing them are worth resolving. When a large number of assertions are to be validated, callbacks save time by eliminating the need to code a new sequence for each scenario. Callbacks also provide more dynamic and fine-grained cont... » read more

PCIe Simulation Speed-Up Using Mentor QVIP With PLDA PCIe Controller For DMA Applications

By Mentor, a Siemens Business - 12 Aug, 2020 - Comments: 0

In this case study, PLDA explains how verification engineers can use Mentor’s Questa Verification IP (QVIP) to improve productivity during the functional verification of PCIe designs with DMA engines. The flexibility of Questa VIP was key to creating custom testbenches from scratch that can dynamically adapt to different IP topologies and configurations, mixing PCIe interfaces with multiple A... » read more

USB4: User Expectations Drive Design Complexity

By Synopsys - 05 Aug, 2020 - Comments: 0

This white paper outlines the capabilities of USB4 Hosts, Hubs, Docks, and Devices with an emphasis on how end-user expectations drive the complexity of USB4 products. USB4 is the most complex USB specification so far and requires designers to understand the USB4, USB 3.2, USB 2.0, USB Type-C, and the USB Power Delivery specifications. Designers must also understand PCIe and DisplayPort specifi... » read more

Power Impact At The Physical Layer Causes Downstream Effects

By Ann Mutschler - 09 Jul, 2020 - Comments: 0

Data movement is rapidly emerging as one of the top design challenges, and it is being complicated by new chip architectures and physical effects caused by increasing density at advanced nodes and in multi-chip systems. Until the introduction of the latest revs of high-bandwidth memory, as well as GDDR6, memory was considered the next big bottleneck. But other compute bottlenecks have been e... » read more

Connecting Emulated Designs To Real PCIe Devices

By Krzysztof Szczur - 28 May, 2020 - Comments: 0

These days verification teams no longer question whether hardware assisted verification should be used in their projects. Rather, they ask at which stage they should start using it. Contemporary System-on-Chip (SoC) designs are already sufficiently complex to make HDL simulation a bottleneck during verification, without even mentioning hardware-software co-verification or firmware and softwa... » read more

Which Chip Interconnect Protocol Is Better?

By Ed Sperling - 11 May, 2020 - Comments: 0

Semiconductor Engineering sat down to the discuss the pros and cons of the Compute Express Link (CXL) and the Cache Coherent Interconnect for Accelerators (CCIX) with Kurt Shuler, vice president of marketing at Arteris IP; Richard Solomon, technical marketing manager for PCI Express controller IP at Synopsys; and Jitendra Mohan, CEO of Astera Labs. What follows are excerpts of that conversation... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: PCIe