Research Bits: July 1


Copper-to-copper bonding for GaN integration Researchers from MIT, Georgia Tech, and Air Force Research Laboratory propose a bonding process to integrate gallium nitride (GaN) transistors onto standard silicon CMOS chips. They used the process to create a power amplifier. “We wanted to combine the functionality of GaN with the power of digital chips made of silicon, but without having to ... » read more

Research Bits: June 9


InGaOx GAA transistor Researchers from the University of Tokyo created a gate-all-around transistor made from gallium-doped indium oxide (InGaOx). Doping indium oxide with gallium suppressed oxygen vacancies, improving transistor reliability. "We wanted our crystalline oxide transistor to feature a 'gate-all-around' structure, whereby the gate, which turns the current on or off, surrounds t... » read more

Chip Industry Technical Paper Roundup: June 3


New technical papers recently added to Semiconductor Engineering’s library: [table id=436 /] Find more semiconductor research papers here. » read more

SRAM Cell Scaling With Monolithic 3D Integration Of 2D FETs (Penn State)


A new technical paper titled "Enabling static random-access memory cell scaling with monolithic 3D integration of 2D field-effect transistors" was published by researchers at The Pennsylvania State University. Abstract "Static Random-Access Memory (SRAM) cells are fundamental in computer architecture, serving crucial roles in cache memory, buffers, and registers due to their high-speed perf... » read more

Chip Industry Technical Paper Roundup: May 20


New technical papers recently added to Semiconductor Engineering’s library: [table id=432 /] Find more semiconductor research papers here. » read more

Floorplanning Method For Reducing Thermally-Induced Structural Stress In Chiplet Packages (Penn State, Intel, ASU et al.)


A new technical paper titled "STAMP-2.5D: Structural and Thermal Aware Methodology for Placement in 2.5D Integration" was published by researchers at Pennsylvania State University, Intel, Arizona State University and University of Notre Dame. Abstract "Chiplet-based architectures and advanced packaging has emerged as transformative approaches in semiconductor design. While conventional ph... » read more

Research Bits: Apr. 29


Microchannels for two-phase cooling Researchers from the University of Tokyo propose cooling chips using microchannels built into the chips themselves. The method utilizes microfluidic channels to create a capillary structure through which coolant flows and a manifold distribution layer that controls the distribution of coolant. The structure enabled two-phase cooling through better managem... » read more

Chip Industry Technical Paper Roundup: Apr. 22


New technical papers recently added to Semiconductor Engineering’s library: [table id=421 /] Find more semiconductor research papers here. » read more

Chip Industry Week In Review


Don't have time to read this? Check out Semiconductor Engineering's Inside Chips podcast.  The U.S. Department of Commerce is investigating TSMC for potential export control violations involving Huawei chips, reports Reuters. The probe follows TechInsights' teardown of a Huawei AI accelerator chip last year. The foundry, meanwhile, maintains it has not shipped any chips to Huawei since 2020... » read more

2D Materials Roadmap: Current And Future Challenges, Solutions


A new technical paper titled "The 2D Materials Roadmap" was published by researchers at many institutions including Chinese Academy of Sciences, TU Denmark, Pennsylvania State University, University of Manchester, University of Cambridge et al. Abstract "Over the past two decades, 2D materials have rapidly evolved into a diverse and expanding family of material platforms. Many members of th... » read more

← Older posts