Nanosheet GAAFETs: Compact Modeling (Politecnico di Torino)


A technical paper titled “NS-GAAFET Compact Modeling: Technological Challenges in Sub-3-nm Circuit Performance” was published by researchers at Politecnico di Torino. Abstract: "NanoSheet-Gate-All-Around-FETs (NS-GAAFETs) are commonly recognized as the future technology to push the digital node scaling into the sub-3 nm range. NS-GAAFETs are expected to replace FinFETs in a few years, as ... » read more

Why Changes In Computing Are Driving Changes In Photomasks


Aki Fujimura, CEO of D2S, talks with Semiconductor Engineering about massive improvements in computation based upon increased density on chips, and why printing Manhattan shapes on a photomask are no longer sufficient to print high-performance devices with predictable reliability every time. He explains why a discontinuity in EDA physical design has opened the door for printing curvilinear shap... » read more

Stress tensor mesostructures for deterministic figuring of thin substrates


New research paper from MIT and University of Arizona, funded by NASA. Abstract "Accessing the immense value of freeform surfaces for mass-sensitive applications such as space optics or metaform optical components requires fabrication processes that are suited to figuring thin substrates. We present stress tensor mesostructures for precisely correcting figure errors, even after microstruc... » read more