Metrology Analysis Tool For Photolithography Process Characterization At Advanced Nodes

By Wolfgang Demmerle - 23 Jul, 2024 - Comments: 0

Continued scaling of integrated circuits to smaller dimensions is still a viable way to increase compute power, achieve higher memory cell density, or reduce power consumption. These days, chip makers are using single-digit nanometer figures or even Angstrom to label their manufacturing technology nodes, which are associated with the size of features patterned during the lithography process. ... » read more

Opportunities Grow For GPU Acceleration

By Gregory Haley - 05 Jun, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss the impact of GPU acceleration on mask design and production and other process technologies, with Aki Fujimura, CEO of D2S; Youping Zhang, head of ASML Brion; Yalin Xiong, senior vice president and general manager of the BBP and reticle products division at KLA; and Kostas Adam, vice president of engineering at Synopsys. W... » read more

Exploring The Fundamentals Of Photolithography

By Joyce Lowes - 23 May, 2024 - Comments: 0

In the semiconductor materials industry, photolithography is a crucial technology for creating intricate electronic circuits. Essentially, it’s the art of printing at the nanoscale level, enabling the precise patterning of semiconductor materials. The ability to do this well is important for companies in the industry because it determines how detailed and efficient microchips can be. This aff... » read more

Nanosheet GAAFETs: Compact Modeling (Politecnico di Torino)

By Technical Paper Link - 07 Jun, 2023 - Comments: 0

A technical paper titled “NS-GAAFET Compact Modeling: Technological Challenges in Sub-3-nm Circuit Performance” was published by researchers at Politecnico di Torino. Abstract: "NanoSheet-Gate-All-Around-FETs (NS-GAAFETs) are commonly recognized as the future technology to push the digital node scaling into the sub-3 nm range. NS-GAAFETs are expected to replace FinFETs in a few years, as ... » read more

Why Changes In Computing Are Driving Changes In Photomasks

By Ed Sperling - 18 Oct, 2022 - Comments: 0

Aki Fujimura, CEO of D2S, talks with Semiconductor Engineering about massive improvements in computation based upon increased density on chips, and why printing Manhattan shapes on a photomask are no longer sufficient to print high-performance devices with predictable reliability every time. He explains why a discontinuity in EDA physical design has opened the door for printing curvilinear shap... » read more

Stress tensor mesostructures for deterministic figuring of thin substrates

By Technical Paper Link - 21 Apr, 2022 - Comments: 0

New research paper from MIT and University of Arizona, funded by NASA. Abstract "Accessing the immense value of freeform surfaces for mass-sensitive applications such as space optics or metaform optical components requires fabrication processes that are suited to figuring thin substrates. We present stress tensor mesostructures for precisely correcting figure errors, even after microstruc... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.