Thermally-Aware, Multi-Objective Scheduling Framework for DL Workloads on Heterogeneous Multi-Chiplet PIM Architectures (UW–Madison, Washington State)


A new technical paper titled "THERMOS: Thermally-Aware Multi-Objective Scheduling of AI Workloads on Heterogeneous Multi-Chiplet PIM Architectures" was published by researchers at the University of Wisconsin–Madison and Washington State University. Abstract "Chiplet-based integration enables large-scale systems that combine diverse technologies, enabling higher yield, lower costs, and sca... » read more

Increasing AI Energy Efficiency With Compute In Memory


Skyrocketing AI compute workloads and fixed power budgets are forcing chip and system architects to take a much harder look at compute in memory (CIM), which until recently was considered little more than a science project. CIM solves two problems. First, it takes more energy to move data back and forth between memory and processor than to actually process it. And second, there is so much da... » read more

A Practical DRAM-Based Multi-Level PIM Architecture For Data Analytics


A technical paper titled "Darwin: A DRAM-based Multi-level Processing-in-Memory Architecture for Data Analytics" was published by researchers at Korea Advanced Institute of Science & Technology (KAIST) and SK hynix Inc. Abstract: "Processing-in-memory (PIM) architecture is an inherent match for data analytics application, but we observe major challenges to address when accelerating it usi... » read more

ETH Zurich: PIM (Processing In Memory) Architecture, UPMEM & PrIM Benchmarks


New paper technical titled "Benchmarking a New Paradigm: An Experimental Analysis of a Real Processing-in-Memory Architecture" led by researchers at ETH Zurich. Researchers provide a comprehensive analysis of the first publicly-available real-world PIM architecture, UPMEM, and introduce PrIM (Processing-In-Memory benchmarks), a benchmark suite of 16 workloads from different application domai... » read more