Chemistry Working For Lithography: The Marangoni-Effect-Based Single Layer For Enhanced Planarization

By Brewer Science - 17 Nov, 2021 - Comments: 0

In the field of semiconductor manufacturing, there is still a continuous search for techniques to improve the Critical Dimension Uniformity (CDU) across the wafer. CDU improvement and general defectiveness reduction increase the industrial yield and guarantee high reliability standards. In the KrF Dual-Damascene module integration, at a lithographic level, deep trench planarization is mandatory... » read more

Development Of Planarizing Spin-On Carbon Materials For High-Temperature Processes

By Brewer Science - 20 Aug, 2020 - Comments: 0

Multilayer lithography is used for advanced semiconductor processes to pattern complex structures. As more and more procedures incorporate a high-temperature process, such as chemical vapor deposition (CVD), the need for thermally stable materials increases. For certain applications, a spin-on carbon (SOC) layer under the CVD layer is required to survive through a high-temperature process. ... » read more

Super Planarizing Material For Trench And Via Arrays

By Brewer Science - 21 May, 2020 - Comments: 0

As device design scales and becomes more complex, fine control of patterning and transfer steps is integral. Planarization of deep trenches and via arrays has always been a challenge. Aspect ratios continue to increase while critical dimensions shrink, and typical trench fill schemes are no longer able to meet the fill and planarization requirements. Traditional design of spin-on carbon (SOC) m... » read more

Planarization Challenges At 7nm And Beyond

By Ed Sperling - 10 Dec, 2018 - Comments: 0

Dan Sullivan, executive director of semiconductor technology at Brewer Science, digs into the challenges of planarizing a thin film on a wafer for etch and optical control. The problem becomes more difficult at advanced nodes because the films are thinner. https://youtu.be/iNA6EGpoYZU _________________________________ See more tech talk videos here » read more

The Problem With Spin-On Carbon Materials

By Runhui Huang - 09 Apr, 2018 - Comments: 0

In an integrated circuit manufacturing process, spin-on-carbon (SOC) materials constitute an important layer for the multilayer process to achieve smaller feature size. The SOC layer responds to the photolithography, pattern transformation, substrate planarization, and a variety of other critical processes. A key challenge in selecting a suitable material is that some processes require a hig... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.