tag: power analysis

FinFET-Based Designs: Package Model Considerations
By Aveek Sarkar - 12 Jun, 2014 - Comments: 0

The use of FinFET devices in next-generation high-performance, low-power designs is a fundamental shift that is happening in the semiconductor industry. These devices through their smaller sizes, tighter Vth control and higher drive strengths enable higher performance and increased integration while reducing overall energy consumption. But along with their advantages these devices introduce and... » read more

Billion-Gate Signoff
By Graham Bell - 30 Jan, 2014 - Comments: 0

At last year’s Design and Verification Conference in San Jose, Real Intent had a tutorial session on “Pre-Simulation Verification for RTL Sign-Off.” This was a start of conversation in the industry that we have seen grow through DAC 2013 in Austin, and which is getting louder each day. Verification companies are now talking about crossing the billion-gate threshold and what can be done to... » read more

Current Generation Of FPGAs Pose New Power And Reliability Challenges
By Annapoorna Krishnaswamy - 07 Nov, 2013 - Comments: 0

Today’s FPGAs are being used in a wide variety of applications such as consumer electronics, computer and storage, automotive electronics, and mission critical applications. The flexibility to configure the device based on its need, the ability to reprogram its functions, and the hardware parallelism it offers to quickly process very large amounts of data are some of the reasons why off-the-s... » read more

Dealing With The Data Glut
By Ann Mutschler - 11 Apr, 2013 - Comments: 0

By Ann Steffora Mutschler Tools like emulation and simulation are an absolute necessity to design and verify today’s complex SoCs, but what happens when you want to do power analysis and the file sizes are too massive for the emulator to handle? Even with an emulator a five-minute mobile phone call could take three months. Understandably, this issue is causing pain to many design teams... » read more

Mining For Data
By Ed Sperling - 09 Aug, 2012 - Comments: 0

By Ann Steffora Mutschler Power analysis accuracy at the RTL design abstraction is a challenging problem. Smaller geometries just make the challenge of predicting accurate RTL power consumption even more difficult, which in turn impacts other design decisions such as power-grid planning and package selection. “It’s one of these things where the earlier you are in the design, even befo... » read more

Getting In the Ballpark
By Ann Mutschler - 09 Aug, 2012 - Comments: 0

I admit it; I still have DAC on the brain. Even though attendance may not have been what the exhibitors would have liked to see, the conference is always a fantastic place to discuss ideas and pick up on trends. One topic I discussed with a number of folks are the challenges associated with design today, from the power-performance balance, 3D stacking to new process nodes and complexity, to nam... » read more

Low-Power Solutions At DAC
By Bhanu Kapoor - 16 Jun, 2011 - Comments: 0

By Bhanu Kapoor Power is the main driver of semiconductor process technology related advances recently. One would expect a similar focus in the electronic design automation industry to help designers implement low power designs. However, the latest DAC in San Diego didn’t give the impression that the EDA industry is thinking likewise, perhaps with the exception of verification aspects of low... » read more

Wanted: ESL Power Design Flow
By Ann Mutschler - 14 Apr, 2011 - Comments: 0

In order to truly incorporate understanding of power at a higher-than-RTL level of abstraction, a new design flow is needed—and it won’t come from just one vendor. Apache believes that tool flow must contain ESL simulation, ESL synthesis to RTL along with RTL power analysis using ESL simulation results. The company maintains that this very approach has been demonstrated successfully by w... » read more

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