tag: power delivery network

Power Delivery Affecting Performance At 7nm
By Brian Bailey - 11 Oct, 2018 - Comments: 4

Complex interactions and dependencies at 7nm and beyond can create unexpected performance drops in chips that cannot always be caught by signoff tools. This isn't for lack of effort. The amount of time spent trying to determine if an advanced-node chip will work after it is fabricated has been rising steadily for several process nodes. Additional design rules handle everything from variation... » read more

I Say ‘High’ [Performance], You Say ‘Low’ [Power]
By Vinay Patwardhan - 10 Aug, 2017 - Comments: 0

“…You say ‘why’, and I say ‘I don’t know…’” Actually, I do know. Everybody loves a high-performance product. Even just hearing that a product is high-performance sets higher expectations than if the product is simply described as “fast” or “powerful.” When it comes to SoC design, “high-performance” refers to a set of designs that run at very high clock freque... » read more

Design For Silicon Success At 7nm
By Annapoorna Krishnaswamy - 01 May, 2017 - Comments: 0

Next-generation automotive, mobile and high-performance computing applications demand the use of 7nm SoCs to deliver greater functionality and higher performance at much lower power. According to Gartner, when compared to 16nm/14nm technology, 7nm offers 35% speed improvement, 65% less power, and 3.3X density improvement. Hence, despite a whopping cost of $271M — per Gartner's estimate — to... » read more

Managing Voltage Drop At 10/7nm
By Ann Mutschler - 13 Apr, 2017 - Comments: 0

Power integrity is becoming a bigger problem at 10/7nm because existing tools such as static analysis no longer are sufficient. Power integrity is a function of static and dynamic voltage drop in the power delivery network. And until recently, static analysis did an effective job in measuring the overall robustness of PDN connectivity. As such, it is a proxy for PDN strength. The problem is ... » read more

Power Impacting Cost Of Chips
By Brian Bailey - 15 Mar, 2017 - Comments: 0

The increase in complexity of the power delivery network (PDN) is starting to outpace increases in functional complexity, adding to the already escalating costs of modern chips. With no signs of slowdown, designers have to ensure that overdesign and margining do not eat up all of the profit margin. The semiconductor industry is used to problems becoming harder at smaller geometries, but unti... » read more

7nm Design Success Starts With Multi-Domain Multi-Physics Analysis
By Arvind Vel - 28 Nov, 2016 - Comments: 1

Companies can benefit from advancements in the latest semiconductor process technology by delivering smaller, faster and lower power products, especially for those servicing mobile, high performance computing and automotive ADAS applications. By using 7nm processes, design teams are able to add a lot more functionality onto a single chip and lower the power consumption by scaling operating volt... » read more

Why Do You Need Chip-Package-System Co-Design And Co-Analysis?
By Youngsoo Lee - 13 Oct, 2016 - Comments: 0

Whether it is the need for sustainable energy, or driving performance while keeping power at bay, or enabling safe and reliable operation of any electronic system, containment of electronic noise — power and signal noise is critical to all of the above. Other factors that impact safe and reliable operation are electromigration (EM), electromagnetic interference (EMI) and mechanical stress ena... » read more

Designing SoC Power Networks
By Brian Bailey - 11 Aug, 2016 - Comments: 0

Designing a power network for a complex SoC is becoming critical for the success of the product, but most chips are still using old techniques that are ill-suited to the latest fabrication technologies, resulting in an expensive, overdesigned product. Not only is the power network as designed too large, but this has several knock-on effects that impact area, timing and power. In the first pa... » read more

SoC Power Grid Challenges
By Brian Bailey - 14 Jul, 2016 - Comments: 7

The consumption of power and dissipation of heat within large SoCs has received a lot of attention recently, but that is only part of the issue. Power also has to be reliably delivered onto and around the system. This is becoming increasingly difficult, and new nodes are adding to the list of challenges. "If we were building chips where there was only a single Vdd and Vss then it is not that... » read more

The Interconnected Web Of Power
By Brian Bailey - 12 Mar, 2015 - Comments: 0

Tradeoffs between area and timing used to follow fairly simple rules. You could improve timing by adding area, and occasionally find an architectural solution that would decrease both at the same time. With physical synthesis the relationship became a little more complicated because an increase in area, say to make a drive larger or add another buffer, might upset the layout. That, in turn, cou... » read more

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