Blog Review: Oct. 24

Inside PDNs; state of photomask market; DDR5 adoption trends.


Arm’s Shidhartha Das digs into Power Delivery Networks with a look at how the specific roles of different components work to provide smooth supply conditions.

In a video, VLSI Research’s Dan Hutcheson chats with D2S CEO Aki Fujimura about the state of the photomask market, EUV optimism, and the most interesting findings from this year’s eBeam Initiative survey.

Synopsys’ Prasad Subudhi K. S. takes a look at how the new CCIX protocol uses PCIe 4.0 to transfer data at speeds up to 25GT/s.

Cadence’s Paul McLellan takes a look at expected adoption trends for DDR5 and why it’s not just a faster implementation of what’s come before.

Mentor’s Tom Fitzpatrick shares some resources for verification of safety-critical designs and how to make verification processes compatible with DO-254 and ISO 26262.

Soitec’s Manuel Sellier explains how body bias can be an important feature in helping deal with the impact of variations and optimization of energy consumption.

SEMI’s Maria Vetrano talks with Cynthia Wright of The MITRE Corporation about why MEMS and sensors suppliers should get to the forefront of cybersecurity to prevent flaws early in the design process.

Intel’s Melvin Greer argues for the need to accelerate AI adoption through workforce development and points to eight areas the U.S. government has prioritized for investment.

And don’t forget to check out the latest blogs from the Manufacturing & Process Technology newsletter:

Editor in Chief Ed Sperling examines whether EUV’s delay and high cost will pay off.

Executive Editor Mark LaPedus questions how long wafer shortages will last.

KLA-Tencor’s Mark Shirey and Janay Camp delve into technologies that have made 3D NAND possible, including complex deposition and etch with angstrom-level precision.

Applied Materials’ Buvna Ayyagari-Sangamalli finds AI is challenging the entire design ecosystem in new ways.

SEMI’s Serena Brischetto contends that while progress is being made toward standardization, advanced MEMS chips still face unique challenges.

Kandou Bus’ Jeff McGuire points to how to optimize chiplet architectures, including reducing in-package loss and trace length.

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