tag: power delivery network

Partition Lines Growing Fuzzy
By Ed Sperling - 26 Feb, 2015 - Comments: 0

For as long as most semiconductor engineers can remember, chips with discrete functions started out on a printed circuit board, progressed into chip sets when it made sense and eventually were integrated onto the same die. The primary motivations behind this trend were performance and cost—shorter distance, fewer mask layers, less silicon. But this equation has been changing over the past ... » read more

Smart Early ASIC Design Prototyping And Analysis
By Sankar Ramachandran - 04 Dec, 2014 - Comments: 0

The Power Delivery Network (PDN) is the backbone of ASIC design. It is used to supply clean power to active circuits in the IC. Voltage drop on the power rails can result in degraded performance, making delivery of noise free supply to all design elements including die, package and PCB, a challenging task. With increasing competition in the market, delivering chips on time with 'first silico... » read more

Power Delivery Network Verification Coverage
By Ansys - 03 Dec, 2014 - Comments: 0

Power grid verification is a challenge, and there are no industry standards for design teams to follow that will verify the power grid for power and signal integrity issues. In other areas there is typically a verification plan with checks to perform, and when successfully completed, the design is then considered verified to proceed to tape-out. Having high coverage in the power grid’s power... » read more

System-Aware SoC Power, Noise And Reliability Sign-Off
By Ansys - 06 Aug, 2014 - Comments: 0

In globally competitive markets for mobile, consumer and automotive electronic systems, the critical success factors are power consumption, performance and reliability. To manage these conflicting requirements, design teams consider multiple options, including the use of advanced process technology nodes — especially FinFET-based devices. These advanced technology nodes allow chips to operate... » read more

Power Delivery Network Verification Coverage
By Various Writers - 09 Apr, 2014 - Comments: 0

This paper presents a methodology for comprehensive power grid verification coverage, including identification of power grid weaknesses early in the design cycle. To view this white paper, click here. » read more

Power Delivery Network (PDN) Verification Coverage
By Various Writers - 15 Jan, 2014 - Comments: 0

This paper presents a methodology for comprehensive power grid verification coverage, including identification of power grid weaknesses early in the design cycle. To download this white paper, click here. » read more

Signal Integrity’s Growing Complexity
By Matt Elmore - 13 Sep, 2012 - Comments: 0

By Matt Elmore While in the market for a memory upgrade recently, I was surprised by the availability of commercial DDR memories. You can get 8GB of DDR3 memory, transferring 17GB/s, relatively inexpensively. The progress in memory design is outstanding. From smartphones to gaming PCs, quick communication between the IC and off-chip memory is key to enabling the performance we demand in the... » read more

New Reliability Issues
By Arvind Vel - 14 Jun, 2012 - Comments: 0

By Arvind Shanmugavel Reliability of ICs is a topic of growing concern with every technology node migration. With the onset of the 20nm process node from different foundries, reliability verification has taken center stage in design kits—and for good reason. Reliability margins have continued to decrease and have reached an inflection point at the 20nm node. The design and EDA communities ha... » read more

Power-Delivery Network Challenges Grow
By Ed Sperling - 04 Nov, 2010 - Comments: 0

By Ann Steffora Mutschler Physics is forcing convergence in the SoC power delivery network, whose job is to ensure that every device on a chip has a robust and stable voltage so it can meet its expected functionality and timing. In the past, chip design, package design and board design were separate disciplines, guard-banded to ensure that all the parts worked well together. Today, given t... » read more

Making Power Delivery Networks Better
By Ann Mutschler - 04 Nov, 2010 - Comments: 0

Careful design of power delivery networks can make the difference in whether a chip manages power effectively or fails completely. This impact of cost and other factors in the design process has not gone unnoticed. Aveek Sarkar, vice president of customer support and product engineering at Apache Design Solutions, pointed to the iPhone as an example, where 50% or more of the bill of material... » read more

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