tag: power intent

Experts At The Table: The Trouble With Low-Power Verification
By Ed Sperling - 29 Mar, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss low-power verification with Leah Clark, associate technical director at Broadcom; Erich Marschner, product marketing manager at Mentor Graphics; Cary Chin, director of marketing for low-power solutions at Synopsys; and Venki Venkatesh, senior director of engineering at Atrenta. What follows are excerpts of that conversat... » read more

Verifying Your Intent
By Ann Mutschler - 21 Mar, 2013 - Comments: 0

Design rule checking (DRC), layout versus schematic (LVS) and electrical rule checking (ERC) are physical verification techniques that are mandatory today to check a design and its structures before manufacturing. Checking electrical characteristics of a design is one thing. Verifying power intent is quite another. And the overlap of the two is an intriguing concept. Case in point: Checking fo... » read more

Experts At The Table: The Trouble With Low-Power Verification
By Ed Sperling - 14 Mar, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss low-power verification with Leah Clark, associate technical director at Broadcom; Erich Marschner, product marketing manager at Mentor Graphics; Cary Chin, director of marketing for low-power solutions at Synopsys; and Venki Venkatesh, senior director of engineering at Atrenta. What follows are excerpts of that conversat... » read more

The Next UPF
By Erich Marschner - 06 Dec, 2012 - Comments: 0

By Erich Marschner If all goes according to schedule, the new version (2.1) of five-year-old Unified Power Format (UPF) standard will be approved by the IEEE early next year. This is good news, because in the five years since UPF was first defined the demand for systems with both longer battery life and more functionality has increased significantly. As just one example: according to Gartner, ... » read more

Hierarchical LP Design 2
By Luke Lang - 11 Aug, 2011 - Comments: 0

By Luke Lang Last month, I discussed two key features of the Common Power Format (CPF) that support hierarchical design methodology: boundary port and macro model. These are commands that need to be written to describe the power intent and drive the tools. Without these commands, it is extremely difficult to do hierarchical design. But with these commands, hierarchical power intent files are n... » read more

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