tag: power management

Connecting AI Accelerators
By Ann Mutschler - 04 Jun, 2025 - Comments: 0

Experts At The Table: Semiconductor Engineering sat down to discuss the various ways that AI accelerators are being applied today with Marc Meunier, director of ecosystem development at Arm; Jason Lawley, director of product marketing for AI IP at Cadence; Paul Karazuba, vice president of marketing at Expedera; Alexander Petr, senior director at Keysight; Steve Roddy, chief marketing office... » read more

Offline RL Framework That Dynamically Controls The GPU Clock And Server Fan Speed To Optimize Power Consumption And Computation Time (KAIST)
By Technical Paper Link - 31 May, 2025 - Comments: 0

A new technical paper titled "Power Consumption Optimization of GPU Server With Offline Reinforcement Learning" was published by researchers at Korea Advanced Institute of Science and Technology (KAIST) and KT Research and Development Center. "Optimizing GPU server power consumption is complex due to the interdependence of various components. Conventional methods often involve trade-offs: in... » read more

Future-proofing AI Models
By Ann Mutschler - 21 May, 2025 - Comments: 0

Experts At The Table: Making sure AI accelerators can be updated for future requirements is becoming essential due to the rapid introduction of new models. Semiconductor Engineering sat down to discuss the challenges of future-proofing these designs with Marc Meunier, director of ecosystem development at Arm; Jason Lawley, director of product marketing for AI IP at Cadence; Paul Karazuba, vic... » read more

AI Accelerators Moving Out From Data Centers
By Ann Mutschler - 15 May, 2025 - Comments: 0

Experts At The Table: The explosion in AI data is driving chipmakers to look beyond a single planar SoC. Semiconductor Engineering sat down to discuss the need for more computing and the expanding role of chiplets with Marc Meunier, director of ecosystem development at Arm; Jason Lawley, director of product marketing for AI IP at Cadence; Paul Karazuba, vice president of marketing at Expedera; ... » read more

Challenges In Managing Chiplet Resources
By Ann Mutschler - 27 Mar, 2025 - Comments: 0

Managing chiplet resources is emerging as a significant and multi-faceted challenge as chiplets expand beyond the proprietary designs of large chipmakers and interact with other elements in a package or system. Poor resource management in chiplets adds an entirely new dimension to the usual power, performance, and area tradeoffs. It can lead to performance bottlenecks, because as chiplets co... » read more

Enhancing Power Reliability Through Design-Stage Layout Optimization
By Jeff Wilson - 19 Dec, 2024 - Comments: 0

As integrated circuit (IC) designs continue to scale, the demand for efficient power management, performance optimization and reliable physical layout modification grows more critical. Meeting these power, performance and area (PPA) targets is essential for ensuring that IC designs operate effectively at advanced process nodes. One of the main challenges for design and verification engineers is... » read more

Power-Aware Test Vector Porting For Production ATE
By Hari Mani - 12 Nov, 2024 - Comments: 0

Power management in contemporary system-on-chip (SoC) designs is almost unimaginably complex. Processors and other chip cores turn on and off as needed. Advanced features such as dynamic voltage and frequency scaling (DVFS) can adjust to changing conditions and incrementally adjust power and performance on the fly. Power management starts from the lowest hardware level of transistor structures ... » read more

Early Architecture Performance and Power Analysis of Multi-Die Designs
By Synopsys - 30 Oct, 2024 - Comments: 0

Despite the clear advantages of multi-die designs, there are numerous new challenges that stand in the way of multi-die design realization. This white paper focuses on those challenges that can be addressed by early architecture exploration of multi-die designs, including: -System pathfinding -Memory utilization and coherency -Power/thermal management Find out how to overcome such chall... » read more

Examining The Impact Of Chip Power Reduction On Data Center Economics
By Noam Brousard - 12 Mar, 2024 - Comments: 1

In the rapidly evolving landscape of data centers, optimizing energy consumption has become a critical focus. In this blog post, we'll delve into the intricacies of power consumption, exploring the economics of three key components: CPUs, GPUs, and AI accelerators, and how the implementation of proteanTecs power reduction solution transforms both power efficiency and computational capabilities... » read more

New Approaches To Sensors And Sensing
By Ed Sperling - 02 Aug, 2023 - Comments: 0

Sensors are becoming more intelligent, more complex, and much more useful. They are being integrated with other sensors in sensor fusion, so a smart doorbell may only wake up when it’s imperative to see who’s at the door, and a microphone may only send alerts when there are cries for help or sounds of glass breaking. Kim Lee, senior director of system applications engineering at Infineon, t... » read more

← Older posts

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy