Developing Effective Design Strategies for Today’s Wearable Devices: Power Management


As the next wave of wearable devices expands into a new class of revolutionary and innovative products, there will be a growing importance placed on the real-time operating system (RTOS) and corresponding middleware. Wearable System-on-Chip (SoC) processors require an operating system optimized for size and performance with power-efficient wireless connectivity options needed for machine-to-mac... » read more

Smaller, Faster, Cheaper


Sometimes the most intriguing market growth comes in “unsexy” applications. Take the mobile market for example. Overall growth rates are cooling, as you’d expect with a maturing market. But in 2020, 1 billion smart phones are expected to ship in the entry-level category. This implies an 8% compounded annual growth rate, making entry mobile the most rapidly expanding mobile market segme... » read more

Gaps In Performance, Power Coverage


The semiconductor industry always has used metrics to define progress, and in areas such as functional verification significant advances have been made. But so far, no effective metrics have been developed for power, performance, or other system-level concerns, which basically means that design teams have to run blind. On the plus side, the industry has migrated from the use of code coverage... » read more

Power Management Techniques For Smart Grid Devices


Energy efficiency is a top concern among developers building connected devices for the smart grid. Initially, the application-centric approach to building a device was used. But today, with sophisticated hardware power management features available on most modern processors, this is no longer the case. What’s needed is an OS-level approach that allows developers to take advantage of the full ... » read more

Verification Quality Comes Into Focus


Across the board, when I talk with people about power management verification or any verification actually, the topic of quality always comes up. The first plan of attack is to look at coverage: how it is managed, how to perform coverage in a more constructed way. Ellie Burns at Mentor Graphics mentioned that because UPF can define all of the states of the system, the states of the power man... » read more

Formal Low-Power Verification Of Power-Aware Designs


Power reduction and management methods are now all pervasive in system- on-chip (SoC) designs. They are used in SoCs targeted at power-critical applications ranging from mobile appliances with limited battery life to big-box electronics that consume large amounts of increasingly expensive power. Power reduction methods are now applied throughout the chip design flow from architectural design th... » read more

Capturing Performance


The challenge of working out the best performance for a given power budget is not a new one, but in many power-sensitive applications, the balance is tricky and requires sophisticated techniques. This is especially true in the media processor market where many systems companies are held back by power, energy and thermal issues. “It's really not a battery problem, it's a thermal problem... » read more

UPF-Driven RTL Power Budgeting For Energy-Efficient Designs


Energy efficiency of devices has become more critical than ever, with shrinking geometries and increased performance requirements of SoCs in applications ranging from mobile, storage, automotive to processors. Power management, therefore, becomes an important part of IP and SoC design methodology. While power management is critical in all design stages, an important aspect of this methodolog... » read more

Are More Processor Cores Better?


Up until the early 2000s, each generation of processor was faster, used more exotic architectures, had deeper pipelines, used more transistors, ran at higher clock frequencies and consumed more power. In fact power was rising faster than performance and led to the extrapolation that within a few generations, processors would run as hot as nuclear reactors. Something had to change, and that c... » read more

Balancing Implementation Time, Complexity, Schedule


Design complexity today is demanding all the creativity a design engineer can muster to figure out the best ways to optimize a design for the power situation the device will be operating under. Advanced techniques are being leveraged, to be sure, but in varying degrees, perhaps in part because these techniques impact the complexity of the design implementation. If there are four or five ... » read more

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