tag: power modeling

Tech Talk: Power Issues Ahead
By Ed Sperling - 31 May, 2012 - Comments: 0

Aveek Sarkar, vice president of technology and support at ANSYS Apache, talks with Low-Power Engineering about growing concerns over electrostatic discharge, electromigration, the impact of stacked die, and the need for power and thermal models. [youtube vid=-7TtszsuZP0] » read more

Traversing The Abstraction Landscape
By Ed Sperling - 10 May, 2012 - Comments: 0

By Ann Steffora Mutschler Back in the early days of semiconductor design engineers could count the number of transistors on their chip with their own two eyes. They designed and worked at the same level of design abstraction when doing the timing analysis. Tools were SPICE-like, maybe abstracted with slightly simpler timing models than the SPICE-level transistor models. Thanks to Moore’... » read more

New Power Standards Ahead
By Ed Sperling - 10 May, 2012 - Comments: 0

By Ed Sperling Standards groups are beginning to look at power and other physical effects much more seriously in the wake of the dueling power formats—UPF and CPF—that have caused angst across the design industry. To put it in perspective, when CPF and UPF were first introduced power was something of an afterthought in design. At 65nm it ceased to be something that could be dealt with l... » read more

ESL Power Models
By Ed Sperling - 10 May, 2012 - Comments: 0

Low-Power Engineering discusses what's missing from the ESL tool chain with Ghislain Kaiser, CEO of Docea Power. [youtube vid=hV5viEgLIvA] » read more

Don’t Forget Test
By Ann Mutschler - 11 Aug, 2011 - Comments: 0

In the modeling of designs for power, engineers make sure to include real system modes and get real activity vectors but, according to Pete Hardee at Cadence, there are a few things they are forgetting. “If the only activity you are using is your simulation test vectors, those are probably pretty unrealistic and that’s a big source of error. One other thing we see—and this is quite imp... » read more

Keeping Models In Sync
By Ed Sperling - 08 Jul, 2010 - Comments: 0

By Ed Sperling Models and higher levels of abstraction have been hailed as the best choice for developing SoCs at advanced process nodes, but at 28nm and beyond even that approach is showing signs of stress. The number of models needed for a complex SoC has been growing at each new process node, which makes it much more difficult to keep them updated and in sync as the design progresses down t... » read more

End User Report: The Case For Formalizing Power Modeling
By Ed Sperling - 17 Sep, 2009 - Comments: 0

While the industry clearly agrees that power modeling is a necessity for next-generation semiconductor design at the transaction level, what is lacking is a standard way to exchange power models. Low-Power Design talked with David Hathaway, Senior Technical Staff Member at IBM Electronic Design Automation and Nagu Dhanwada, Senior R&D Engineer and Team Lead for Chip Level Power Analysis T... » read more

Moore’s Law vs. Low Power
By Ed Sperling - 17 Sep, 2009 - Comments: 0

By Ed Sperling Moore’s Law and low-power engineering are natural-born enemies, and this dissension is becoming more obvious at each new process node as the two forces are pushed closer together. The basic problem is that shrinking transistors and line widths between wires opens up far more real estate on a chip, which encourages chip architects and marketing chiefs at chipmakers to take... » read more

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