tag: PPA

Risks Rise As Robotic Surgery Goes Mainstream
By John Koon - 30 Jun, 2022 - Comments: 1

As robotic-assisted surgery moves into the mainstream, so do concerns about security breaches, latency, and system performance. In the operating room, every second is critical, and technology failures or delays can be life-threatening. Robotic-assisted surgery (RAS) has around for a couple decades, but it is becoming more prevalent and significantly more complex. The technology often include... » read more

Why Hardware-Dependent Software Is So Critical
By Brian Bailey - 23 Jun, 2022 - Comments: 0

Hardware and software are two sides of the same coin, but they often live in different worlds. In the past, hardware and software rarely were designed together, and many companies and products failed because the total solution was unable to deliver. The big question is whether the industry has learned anything since then. At the very least, there is widespread recognition that hardware-depen... » read more

Improving PPA With AI
By John Koon - 12 May, 2022 - Comments: 0

AI/ML/DL is starting to show up in EDA tools for a variety of steps in the semiconductor design flow, many of them aimed at improving performance, reducing power, and speeding time to market by catching errors that humans might overlook. It's unlikely that complex SoCs, or heterogeneous integration in advanced packages, ever will be perfect at first silicon. Still, the number of common error... » read more

Optimizing NoC-Based Designs
By Paul Graykowski - 05 May, 2022 - Comments: 0

Semiconductor development is currently in a phase of rapid evolution driven by the combination of new technologies and methodologies. The technique of combining multiple functions into systems-on-chips (SoCs) is continuing to grow in complexity. Rapid advancement in new technologies for market segments like data centers, robotics, ADAS and artificial intelligence/machine learning (AI/ML) are re... » read more

Planning EDA’s Next Steps
By Ed Sperling - 24 Mar, 2022 - Comments: 0

Anirudh Devgan, Cadence's new CEO, and the recipient of the Phil Kaufman Award in December, sat down with Semiconductor Engineering to talk about what's next in EDA, the underlying technology and business challenges and changes, and new markets that are unfolding for floor-planning, verification, CFD, and advanced packaging. SE: Where does EDA need to improve? Devgan: We have made it much... » read more

Improving PPA In Complex Designs With AI
By John Koon - 14 Feb, 2022 - Comments: 0

The goal of chip design always has been to optimize power, performance, and area (PPA), but results can vary greatly even with the best tools and highly experienced engineering teams. Optimizing PPA involves a growing number of tradeoffs that can vary by application, by availability of IP and other components, as well as the familiarity of engineers with different tools and methodologies. Fo... » read more

Meeting Processor Performance And Safety Requirements For New ADAS & Autonomous Vehicle Systems
By Fergus Casey - 02 Dec, 2021 - Comments: 1

By Fergus Casey and Srini Krishnaswami Innovation in today’s automotive industry is accelerating as companies race to be the market leader in safety and autonomous vehicles. With vehicle control moving from humans to the vehicles’ active safety systems, more sensors – cameras, radar, lidar, etc. – are being added to automotive systems. More sensors require more computational performa... » read more

Aprisa Place-And-Route For Low-Power SoCs
By Siemens EDA - 10 Nov, 2021 - Comments: 0

The Aprisa digital design software helps designers address the many challenges of low-power designs. Aprisa is the most flexible IC place-and-route tool on the market—it accepts all industry-standard power formats, has excellent correlation to third-party signoff tools, and is easy to install, set up, and use. With effective technology and impressive usability, the Aprisa software ensures cos... » read more

PPA(V): Performance-Per-Watt Optimization With Variable Operating Voltage
By Synopsys - 10 Nov, 2021 - Comments: 0

Performance-per-watt has emerged as one of the highest priorities in design quality, leading to a shift in technology focus and design power optimization methodologies. Variable operating voltage possess high potential in optimizing performance-per-watt results but requires a signoff accurate and efficient methodology to explore. Synopsys Fusion Design Platform, uniquely built on a singular RTL... » read more

HBM3: Big Impact On Chip Design
By Ann Mutschler - 14 Oct, 2021 - Comments: 0

An insatiable demand for bandwidth in everything from high-performance computing to AI training, gaming, and automotive applications is fueling the development of the next generation of high-bandwidth memory. HBM3 will bring a 2X bump in bandwidth and capacity per stack, as well as some other benefits. What was once considered a "slow and wide" memory technology to reduce signal traffic dela... » read more

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