中文 English

eFPGAs Bring A 10X Advantage In Power And Cost

Eliminate additional packaging and SerDes costs by integrating FPGA into an SoC.

popularity

eFPGA LUTs will out-ship FPGA LUTs at some point in the near future because of the advantages of reconfigurable logic being built into the chip: cost reduction, lower power, and improved performance.

Many systems use FPGAs because they are more efficient than processors for parallel processing and can be programmed with application specific co-processors or accelerators typically found in datacenters, wireless base stations, and enterprise storage.

The need for improved processing in the cloud is driven by faster search results, which drives revenue and power reduction. The area, power, and cost of FPGAs are driving system architects and their design partners to look for a better solution. The solution that is being adopted is integrating FPGAs into the main SoC.

Why? Because it saves power and cost by as much as 10X. The 10X in cost reduction does not even include the saving from inventory reduction and testing when there is an extra chip on the board. Integrating the FPGA can reduce costs from $300 down to $20 of additional silicon cost, and the power similarly.

Fig. 1: eFPGA cuts power and cost by as much as 10X.

In figure 1, we break down the process to assess how to maximize the cost and power reduction for a processor + FPGA processing solution.  As most chip designers know, packaging is a significant cost of each chip. Integrating the FPGA removes the packaging cost. Savings could be as much as 40% of the cost of the FPGA chip, which range from tens to hundreds of dollars. In an integrated solution, only one chip needs to be packaged, which is already factored into the cost of the main processing SoC. Normally in the pricing of chips, everything is marked up, including packaging. FPGAs are no different, so conservatively we did not include that.

Next, we can remove the SerDes in the FPGA as these are not needed anymore because there is no separate FPGA chip. All the communication between the eFPGA and processor subsystem will happen directly within the SoC. Analog I/O devices used in the FPGA chip are no longer present, which can be a large reduction in cost and an even larger savings in power. Also, without the signals having to travel through a SerDes on both sides, latency is reduced. This can be critical for some applications such as searches and data look-ups where latency through one high-speed SerDes can be as much as 20-30 clock cycles. Since the SerDes inside the SoC is also not needed, the latency reduction is double that!

In every FPGA design, there is logic that does not change. But since you have a single FPGA for much of the design, it’s easier to include the entire design as one big blob into a sea of LUTS. SoC integration and eFPGA provide an opportunity to rethink how the FPGA design is partitioned so you can leverage the area, power, and performance benefits of ASIC gates by putting those fixed logic components into the SoC as hardwired logic. This can be conservatively estimated at 20% of the silicon area, but some designs will have more savings of cost and power.

Technology is getting smaller and smaller, and this is providing the opportunity to reduce the total cost of ownership by going to smaller nodes. Embedded FPGA made with 100% standard cells can be ported quickly to reduce area, cost, and power of the final SoC, as noted in the figure. This is at a pace that is much faster than FPGA providers, who utilize SRAM memory cells and do full custom design, which can take several years to move to a new technology node.

Flex Logix provides a hard macro that sits in the lower layers of the metal stack and is compatible to most metal stacks offered in a foundry’s process. Flex Logix eFPGAs save power and area using our patented Boundless Radix interconnect. This interconnect results in shorter paths, less area, and higher utilization of the eFPGA. Also, we can offer different types of power gating to lower power even further. By proving a completely hardened design, we simplify the closing of timing for the customer and ease their integration of the eFPGA.

So the next time you are looking to reduce cost and power in your system, think about including eFPGA. And for the most power reduction and ease of integration, think EFLX eFPGAs from Flex Logix.



Leave a Reply


(Note: This name will be displayed publicly)