Which Process, Material, IP?

By Ed Sperling - 30 Jul, 2015 - Comments: 1

For years chipmakers have been demanding more choices. They've finally gotten what they wished for—so many possibilities, in fact, that engineering teams of all types are having trouble wading through them. And to make matters worse, some choices now come with unexpected and often unwanted caveats. At the most advanced nodes it's a given that being able to shrink features and double patter... » read more

IP Integration Challenges Increase

By Ed Sperling - 08 Jul, 2015 - Comments: 0

Semiconductor Engineering sat down with Chris Rowen, CTO of [getentity id="22032" e_name="Cadence"]'s IP group; Rob Aitken, an [getentity id="22186" comment="ARM"] fellow; Patrick Soheili, vice president of product management and corporate development at [getentity id="22242" e_name="eSilicon"]; Navraj Nandra, senior director of marketing for DesignWare analog and mixed-signal IP at [getentity ... » read more

One-On-One: Thomas Caulfield

By Mark LaPedus - 21 May, 2015 - Comments: 0

Semiconductor Engineering sat down to talk about fabs, process technology and the equipment industry with Thomas Caulfield, senior vice president and general manager of Fab 8 at [getentity id="22819" comment="GlobalFoundries"]. Located in Saratoga County, N.Y., Fab 8 is GlobalFoundries’ most advanced 300mm wafer fab. What follows are excerpts of that discussion. SE: Last year, GlobalFoundr... » read more

FD-SOI Vs. FinFETs

By Ed Sperling - 13 May, 2015 - Comments: 3

Semiconductor Engineering sat down to compare the benefits, risks and challenges of moving to finFETs compared with fully depleted silicon on insulator ([getkc id="220" kc_name="FD-SOI"]) with Philippe Magarshack, group vice president for technology R&D at [getentity id="22331" comment="STMicroelectronics"]; Marco Brambilla, director of engineering at [getentity id="22150" e_name="Synapse D... » read more

FD-SOI Vs. FinFETs

By Ed Sperling - 16 Apr, 2015 - Comments: 1

TSMC Tech Tour De Force

By Barry Pangrle - 13 Apr, 2015 - Comments: 0

TSMC held the first of its three North American Tech Symposiums on April 7 in San Jose, with the other two coming up in Boston on April 14 and in Austin on April 16. As was mentioned previously here, the record fast ramp-time of the 20nm node was highlighted among other technological achievements. TSMC also released its March revenue report on April 10, and it shows a dramatic 49.8% increase in... » read more

Redefining Progress

By Ed Sperling - 22 Jan, 2015 - Comments: 0

After lots of wrangling over the whether Moore's Law is alive, dead, or languishing at somewhere in between, that discussion now seems about as relevant as the look and feel of Apple's early Macintosh operating system—an issue that back in the 1980s spawned a very public war with Microsoft. Today that argument is about as relevant as whether Betamax was better than VHS. Whether it's Moor... » read more

And the Winner is…

By Brian Bailey - 18 Dec, 2014 - Comments: 0

Semiconductor Engineering now has its first full year under its belt, and I have to say it has been an incredible year. Not only did we exceed a million page views in our first year, but we also got started on the Knowledge Center, an endeavor the likes of which has never been attempted in our industry. It is still very young and has a lot of growing up to do, but it is a wonderful start. We wo... » read more

More Than Moore

By Ed Sperling - 15 Sep, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss the value of feature shrinks and what comes next with Steve Eplett, design technology and automation manager at [getentity id="22664" e_name="Open-Silicon"]; Patrick Soheili, vice president and general manager of IP Solutions at [getentity id="22242" e_name="eSilicon"]; Brandon Wang, engineering group director at [getentity id="22032" e_name="Cadenc... » read more

1-on-1 With Intel’s Foundry Chief

By Mark LaPedus - 17 Jul, 2014 - Comments: 1

By Mark LaPedus & Ed Sperling Semiconductor Engineering sat down to discuss foundry trends, IC scaling, chip-packaging and other topics with Sunit Rikhi, vice president of the Technology and Manufacturing Group at Intel and general manager of Intel’s Custom Foundry unit. SE: Where is Intel at in the foundry business today? Rikhi: We started with a very narrow set of customers. Now, we... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: process technology

Which Process, Material, IP?

IP Integration Challenges Increase

One-On-One: Thomas Caulfield

FD-SOI Vs. FinFETs

FD-SOI Vs. FinFETs

TSMC Tech Tour De Force

Redefining Progress

And the Winner is…

More Than Moore

1-on-1 With Intel’s Foundry Chief