7/5nm Timing Closure Intensifies

By Ann Mutschler - 25 Jan, 2018 - Comments: 1

Timing closure issues are increasing in magnitude at 7/5nm, and ones that were often considered minor in the past no longer can be ignored. Timing closure is an essential part of any chip design. The process ensures that all combinatorial paths through a design meet the necessary timing so that it can run reliably at a specified clock rate. Timing closure hasn't changed significantly over th... » read more

Tech Talk: 7nm Process Variation

By Ed Sperling - 17 Jan, 2018 - Comments: 0

Ankur Gupta, director of field applications at ANSYS, discusses process variation and the problems it can cause at 10/7nm and beyond. https://youtu.be/WHNjFr1Da6s » read more

The Next 5 Years Of Chip Technology

By Ed Sperling - 15 Jan, 2018 - Comments: 1

Semiconductor Engineering sat down to discuss the future of scaling, the impact of variation, and the introduction of new materials and technologies, with Rick Gottscho, CTO of [getentity id="22820" comment="Lam Research"]; Mark Dougherty, vice president of advanced module engineering at [getentity id="22819" comment="GlobalFoundries"]; David Shortt, technical fellow at [getentity id="22876" co... » read more

The Implementation Of Embedded PVT Monitoring Subsystems In Today’s Cutting Edge Technologies

By Moortec - 13 Dec, 2017 - Comments: 0

This new whitepaper from Moortec takes a comprehensive look at the Implementation of Embedded PVT Monitoring Subsystems in Today’s Cutting Edge Technologies and how this can benefit today’s advanced node semiconductor design engineers by improving the performance and reliability of SoC designs. With advances in CMOS technology, and the scaling of transistor channel lengths to nanometer (nm)... » read more

Variation Spreads At 10/7nm

By Ed Sperling - 16 Nov, 2017 - Comments: 6

Variation between different manufacturing equipment is becoming increasingly troublesome as chipmakers push to 10/7nm and beyond. Process variation is a well-known phenomenon at advanced nodes. But some of that is actually due to variations in equipment—sometimes the exact same model from the same vendor. Normally this would fall well below the radar of the semiconductor industry. But as t... » read more

Tech Talk: Near-Threshold Power

By Ed Sperling - 13 Nov, 2017 - Comments: 2

Lauri Koskinen, CTO and founder of Minima Processor, and Ron Moore, vice president of marketing at ARM, talk about near-threshold computing, dynamic power and margining, and how these techniques can extend battery life and reduce energy consumption. https://youtu.be/BhiNFe4NYQU » read more

22nm Process War Begins

By Mark LaPedus - 23 Apr, 2017 - Comments: 1

Many foundry customers at the 28nm node and above are developing new chips and are exploring the idea of migrating to 16nm/14nm and beyond. But for the most part, those companies are stuck because they can’t afford the soaring IC design costs at advanced nodes. Seeking to satisfy a potential gap in the market, [getentity id="22819" comment="GlobalFoundries"], [getentity id="22846" e_name="... » read more

The Future Of Memory

By Ed Sperling - 24 Aug, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss future memory with Frank Ferro, senior director of product management for memory and interface IP at Rambus; Marc Greenberg, director of product marketing at Synopsys; and Lisa Minwell, eSilicon's senior director of IP marketing. What follows are excerpts of that conversation. To view part 1, click here. Part 2 is here. SE: What’s the next big ... » read more

Modeling Semiconductor Process Variation

By Coventor - 21 Apr, 2016 - Comments: 0

3D semiconductors, 3D NAND Flash, FinFETS and other advanced devices are bringing tremendous opportunities to the semiconductor industry. Unfortunately, these devices are also bringing new design, process and production problems. Process variability has been a major contributor to production delays as feature sizes have decreased and process complexity has increased. Virtual fabrication is a co... » read more

Transistor-Level Verification Returns

By Brian Bailey - 13 Jan, 2016 - Comments: 1

A few decades ago, all designers did transistor-level verification, but they were quite happy to say goodbye to it when standard cells provided isolation at the gate-level and libraries provided all of the detailed information required, such as timing. A few dedicated people continued to use the technology to provide those models and libraries and the most aggressive designs that wanted to stri... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: process variation