Week In Review: Semiconductor Manufacturing, Test

By Karen Heyman - 03 Feb, 2023 - Comments: 0

Imec released its semiconductor roadmap, which calls for doubling compute power every six months to handle the data explosion and new data-intensive problems. Imec named five walls (scaling, memory, power, sustainability, cost) that need to be dismantled. The roadmap (below) stretches from 7nm to 0.2nm (2 angstroms) by 2036, and includes four generations of gate-all-around FETs followed by thre... » read more

The Path To Known Good Interconnects

By Laura Peters - 19 Jan, 2023 - Comments: 1

Chiplets and heterogenous integration (HI) provide a compelling way to continue delivering improvements in performance, power, area, and cost (PPAC) as Moore’s Law slows, but choosing the best way to connect these devices so they behave in consistent and predictable ways is becoming a challenge as the number of options continues to grow. More possibilities also bring more potential interac... » read more

Heterogeneous Integration: Fertile Ground For Medical And Biotech Innovation

By Promex Industries - 18 Jan, 2023 - Comments: 0

Sensing components in medical and biotech devices often place severe restrictions on the assembly methods that can be employed, which is part of what is driving heightened demand for heterogeneous integration (HI). It is the newest frontier for the medical and biotech manufacturing services industry to contribute our own innovations by developing the processes to build these unique combinations... » read more

Heterogeneous Assembly Datasheet

By Promex Industries - 16 Dec, 2022 - Comments: 0

Medical and biotech devices often include optical, chemical, RF, and liquid elements. Some are combined with electronic devices to increase functionality or interaction with the environment. To produce these devices, multiple technologies are combined in a cost-effective way, ideally using a rapid process development cycle to minimize time to market. Combining technologies, as well as combining... » read more

Hot Trends In Semiconductor Thermal Management

By Karen Heyman - 17 Nov, 2022 - Comments: 1

Increasing thermal challenges, as the industry moves into 3D packaging and continues to scale digital logic, are pushing the limits of R&D. The basic physics of having too much heat trapped in too small a space is leading to tangible problems, like consumer products that are too hot to hold. Far worse, however, is the loss of power and reliability, as overheated DRAM has to continually r... » read more

Heterogeneous Assembly

By Promex Industries - 16 Nov, 2022 - Comments: 0

Bump Co-Planarity And Inconsistencies Cause Yield, Reliability Issues

By Karen Heyman - 11 Oct, 2022 - Comments: 0

Bumps are a key component in many advanced packages, but at nanoscale levels making sure all those bumps have a consistent height is an increasing challenge. Without co-planarity, surfaces may not properly adhere. That can reduce yield if the problem is not identified in packaging, or it can cause reliability problems in the field. Identifying those issues requires a variety of process steps... » read more

Heterogeneous Integration Device Assembly: Key To Enabling Additional Innovations

By Dick Otte - 18 Aug, 2022 - Comments: 0

Heterogeneous integration (HI) improves device functionality by expanding the types of parts and physical configurations combined with silicon chips. Different parts add new functions – with minimal additional volume – thus increasing overall functionality per unit volume. By comparison, classic methods employed to build electronic products, e.g., circuit boards or metal boxes, increase pro... » read more

Variation Making Trouble In Advanced Packages

By Ed Sperling - 16 Jun, 2022 - Comments: 2

Variation is becoming increasingly problematic as chip designs become more heterogeneous and targeted by application, making it difficult to identify the root cause of problems or predict what can go wrong and when. Concerns about variation traditionally have been confined to the most advanced nodes, where transistor density is highest and where manufacturing processes are still being fine-t... » read more

Week in Review: Manufacturing, Test

By Linda Christensen - 13 May, 2022 - Comments: 0

Industry Numbers NAND flash memory is forecast to hit US $83 billion this year, an increase of 24%. DRAM is projected to hit $118 billion, up 25%, according to a recent Yole report. Both are historic records. DRAM and NAND revenues are expected to be a $260 billion market in 2027 (combined), with advanced technologies such as EUV lithography, hybrid bonding and 3D DRAM driving this. SEMI in... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?