The Role Of NoCs In System-Level Services

By Kurt Shuler - 03 Sep, 2020 - Comments: 0

The primary objective of any network-on-chip (NoC) interconnect is to move data around a chip as efficiently as possible with as little impact as possible on design closure while meeting or exceeding key design metrics (PPA, etc.). These networks have become the central nervous system of SoCs and are starting to play a larger role in system-level services like quality of service (QoS), debug, p... » read more

Optimizing DDR Memory Subsystem Efficiency

By Synopsys - 23 Mar, 2016 - Comments: 0

This whitepaper applies virtual prototyping tools and best practice techniques to optimize the DDR memory subsystem configuration for a specific SoC application. Starting from a hypothetical Mobile Application Processor design, we will illustrate step-by step how to optimize: Address mapping Clock frequency Quality of Service (QoS) To read more, click here. » read more

Optimizing Enterprise-Class SSD Host Controller Design With Arteris FlexNoC Network-On-Chip Interconnect IP

By Arteris - 26 Feb, 2016 - Comments: 0

Solid state storage is rapidly supplanting rotary storage in data center computing, driven by the competing needs for lower power consumption, lower latency and higher bandwidth. But the inherent unreliability of flash cells mandates the use of sophisticated host controllers to guarantee data reliability and endurance for enterprise solid state disks (SSD). Leading enterprise SSD companies have... » read more

NoC Reliability: Simplified

By Randy Smith - 26 Mar, 2015 - Comments: 0

Recently, the reliability features of on-chip network (NoC) IP have received much attention. One reason for this focus has been the rush of companies to get into the automotive electronics market and the explosion of new automotive features being implemented in electronic systems. While the details may vary, the high-level view of on-chip network reliability is really quite simple. At the ar... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: QoS

The Role Of NoCs In System-Level Services

Optimizing DDR Memory Subsystem Efficiency

Optimizing Enterprise-Class SSD Host Controller Design With Arteris FlexNoC Network-On-Chip Interconnect IP

NoC Reliability: Simplified