Prevent AI Hardware Obsolescence And Optimize Efficiency With eFPGA Adaptability

By Jayson Bethurem - 01 Aug, 2024 - Comments: 0

Large Language Models (LLMs) and Generative AI are driving up memory requirements, presenting a significant challenge. Modern LLMs can have billions of parameters, demanding many gigabytes of memory. To address this issue, AI architects have devised clever solutions that dramatically reduce memory needs. Evolving techniques like lossless weight compression, structured sparsity, and new numer... » read more

On-Device Speaker Identification For Digital Television (DTV)

By Marcus Corbin - 18 Jul, 2024 - Comments: 0

In recent years, the way we interact with our TVs has changed. Multiple button presses to navigate an on-screen keyboard have been replaced with direct interaction through our voices. While this has resulted in significant improvements to the Digital Television (DTV) user experience, more can be done to provide immersive and engaging experiences. Imagine you say, “recommend me a film” or... » read more

High-Level Synthesis Propels Next-Gen AI Accelerators

By Russell Klein - 20 May, 2024 - Comments: 0

Everything around you is getting smarter. Artificial intelligence is not just a data center application but will be deployed in all kinds of embedded systems that we interact with daily. We expect to talk to and gesture at them. We expect them to recognize and understand us. And we expect them to operate with just a little bit of common sense. This intelligence is making these systems not just ... » read more

Embrace The New!

By Steve Roddy - 14 Mar, 2024 - Comments: 0

The ResNet family of machine learning algorithms was introduced to the AI world in 2015. A slew of variations was rapidly discovered that at the time pushed the accuracy of ResNets close to the 80% threshold (78.57% Top 1 accuracy for ResNet-152 on ImageNet). This state-of-the-art performance at the time, coupled with the rather simple operator structure that was readily amenable to hardware ac... » read more

BYO NPU Benchmarks

By Steve Roddy - 14 Dec, 2023 - Comments: 0

In our last blog post, we highlighted the ways that NPU vendors can shade the truth about performance on benchmark networks such that comparing common performance scores such as “Resnet50 Inferences / Second” can be a futile exercise. But there is a straight-forward, low-investment method for an IP evaluator to short-circuit all the vendor shenanigans and get a solid apples-to-apples result... » read more

Neural Network Model Quantization On Mobile

By Roberto Lopez Mendez - 09 Nov, 2023 - Comments: 0

The general definition of quantization states that it is the process of mapping continuous infinite values to a smaller set of discrete finite values. In this blog, we will talk about quantization in the context of neural network (NN) models, as the process of reducing the precision of the weights, biases, and activations. Moving from floating-point representations to low-precision fixed intege... » read more

Object Detection CNN Suitable For Edge Processors With Limited Memory

By Technical Paper Link - 14 Jun, 2023 - Comments: 0

A technical paper titled “TinyissimoYOLO: A Quantized, Low-Memory Footprint, TinyML Object Detection Network for Low Power Microcontrollers” was published by researchers at ETH Zurich. Abstract: "This paper introduces a highly flexible, quantized, memory-efficient, and ultra-lightweight object detection network, called TinyissimoYOLO. It aims to enable object detection on microcontrol... » read more

Training a ML model On An Intelligent Edge Device Using Less Than 256KB Memory

By Technical Paper Link - 11 Oct, 2022 - Comments: 0

A new technical paper titled "On-Device Training Under 256KB Memory" was published by researchers at MIT and MIT-IBM Watson AI Lab. “Our study enables IoT devices to not only perform inference but also continuously update the AI models to newly collected data, paving the way for lifelong on-device learning. The low resource utilization makes deep learning more accessible and can have a bro... » read more

Convolutional Neural Networks: Co-Design of Hardware Architecture and Compression Algorithm

By Technical Paper Link - 07 Sep, 2022 - Comments: 0

Researchers at Soongsil University (Korea) published "A Survey on Efficient Convolutional Neural Networks and Hardware Acceleration." Abstract: "Over the past decade, deep-learning-based representations have demonstrated remarkable performance in academia and industry. The learning capability of convolutional neural networks (CNNs) originates from a combination of various feature extraction... » read more

Transforming AI Models For Accelerator Chips

By Ed Sperling - 17 May, 2022 - Comments: 0

AI is all about speeding up the movement and processing of data. Ali Cheraghi, solution architect at Flex Logix, talks about why floating point data needs to be converted into integer point data, how that impacts power and performance, and how different approaches in quantization play into this formula. » read more

← Older posts

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?