tag: Rambus

Moving Data And Computing Closer Together
By Bryon Moyer - 09 Jul, 2020 - Comments: 2

The speed of processors has increased to the point where they often are no longer the performance bottleneck for many systems. It's now about data access. Moving data around costs both time and power, and developers are looking for ways to reduce the distances that data has to move. That means bringing data and memory nearer to each other. “Hard drives didn't have enough data flow to cr... » read more

Power Impact At The Physical Layer Causes Downstream Effects
By Ann Mutschler - 09 Jul, 2020 - Comments: 0

Data movement is rapidly emerging as one of the top design challenges, and it is being complicated by new chip architectures and physical effects caused by increasing density at advanced nodes and in multi-chip systems. Until the introduction of the latest revs of high-bandwidth memory, as well as GDDR6, memory was considered the next big bottleneck. But other compute bottlenecks have been e... » read more

The Evolution Of Ethernet To 800G And MACsec Encryption
By Maxim Demchenko - 01 Jul, 2020 - Comments: 0

Ethernet is a frame-based data communication technology that employs variable-sized frames to carry a data payload. This contrasts with long-haul Optical Transport Networks (OTN) that use fixed-sized frames. The size of Ethernet frames ranges from a minimum of 60 bytes up to 1500 bytes, and in case of jumbo frames, up to 9K bytes. A frame is a Layer 2 data container with the physical addresses ... » read more

Winners And Losers At The Edge
By Ed Sperling - 01 Jul, 2020 - Comments: 0

The edge is a vast collection of niches tied to narrow vertical markets, and it is likely to stay that way for years to come. This is both good and bad for semiconductor companies, depending upon where they sit in the ecosystem and their ability to adapt to a constantly shifting landscape. Some segments will see continued or new growth, including EDA, manufacturing equipment, IP, security an... » read more

Blog Review: June 30
By Jesse Allen - 30 Jun, 2020 - Comments: 0

Cadence's Paul McLellan examines Fully Homomorphic Encryption, which allows for operations to be performed on encrypted data without decrypting it, and why it's now entering the realm of practicality. Mentor's Shivani Joshi explains the basics of using keepouts to prevent the placement of specific or all design items within a specified area and why they can make or break a first pass at crea... » read more

Blog Review: June 24
By Jesse Allen - 24 Jun, 2020 - Comments: 0

Cadence's Paul McLellan provides an overview of the new IEEE 1838 standard for manufacturing test of 3D stacked ICs and how it aims to enable testing of multi-die chiplet-based designs. In a video, Mentor's Colin Walls investigates the scope and lifetime of pointers in embedded applications. A Synopsys writer checks out the latest mobile memory standard, JESD209-5A, and the enhancements i... » read more

What’s After PAM-4?
By Bryon Moyer - 23 Jun, 2020 - Comments: 1

[This is part 2 of a 2-part series. Part 1 can be found here.] The future of high-speed physical signaling is uncertain. While PAM-4 remains one of the key standards today, there is widespread debate about whether PAM-8 will succeed it. This has an impact on everything from where the next bottlenecks are likely to emerge and the best approaches to solving them, to how chips, systems and p... » read more

Week In Review: Design, Low Power
By Jesse Allen - 19 Jun, 2020 - Comments: 0

Tools & IP Rambus debuted 112G XSR/USR PHY IP on TSMC's N7 7nm process. The PHY IP enables die-to-die and die-to-optical engine connectivity for chiplets and co-packaged optics targeting data center, networking, 5G, HPC, and AI/ML applications. It has been demonstrated in silicon to exceed the reach/BER performance of the CEI-112G XSR specification and supports NRZ and PAM-4 signaling at v... » read more

Week In Review: Auto, Security, Pervasive Computing
By Susan Rambo - 19 Jun, 2020 - Comments: 0

Security Many IoT devices have some of the 19 bugs known as Ripple20 vulnerabilities. Researchers JSOF discovered the security flaws in library produces by Treck, Inc., which is used in many IoT devices. Edge, cloud, data center Rambus delivered its 112G XSR/USR PHY IP on TSMC 7nm process (N7). The SerDes PHY was designed for chiplets and co-packaged optics (CPO) architectures that are des... » read more

High-Speed Signaling Drill-Down
By Bryon Moyer - 17 Jun, 2020 - Comments: 0

Chip interconnect standards have received a lot of attention lately, with parallel versions proliferating for chiplets and serial versions moving to higher speeds. The lowliest characteristic of these interconnect schemes is the physical signaling format. Having been static at NRZ (non-return-to-zero) for decades, change is underway. “Multiple approaches are likely to emerge,” said Brig ... » read more

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