Gearing Up For Hybrid Bonding

By Laura Peters - 23 Oct, 2023 - Comments: 2

Hybrid bonding is becoming the preferred approach to making heterogeneous integration work, as the semiconductor industry shifts its focus from 2D scaling to 3D scaling. By stacking chiplets vertically in direct wafer-to-wafer bonds, chipmakers can leapfrog attainable interconnection pitch from 35µm in copper micro-bumps to 10µm or less. That reduces signal delay to negligible levels and e... » read more

Measurement Of Deep Trenches To Study The RIE Lag Effect

By KLA - 07 Jun, 2022 - Comments: 0

The demand for accurate characterization of high aspect ratio geometries such as narrow gaps, deep trenches or deep holes arises in many technologies and industries. A variety of metrology techniques have been utilized to accommodate these needs. Among the candidates for this type of metrology, 3D optical profiling characterization is becoming more and more prevalent in process control. Due to ... » read more

Demand, Lead Times Soar For 300mm Equipment

By Mark LaPedus - 20 May, 2021 - Comments: 0

A surge in demand for various chips is causing select shortages and extended lead times for many types of 300mm semiconductor equipment, photomask tools, wafers, and other products. For the last several years, 200mm equipment has been in short supply in the market, but issues are now cropping up throughout the 300mm supply chain, as well. Traditionally, lead times have been three to six mont... » read more

NVM Reliability Challenges And Tradeoffs

By Bryon Moyer - 13 Apr, 2020 - Comments: 0

This second of two parts looks at different memories and possible solutions. Part one can be found here. While various NVM technologies, such as PCRAM, MRAM, ReRAM and NRAM share similar high-level traits, their physical renderings are quite different. That provides each with its own set of challenges and solutions. PCRAM has had a fraught history. Initially released by Samsung, Micron, a... » read more

Deprocessing And SEM For Semiconductor Failure Analysis

By Helle Ronsberg - 09 Jul, 2019 - Comments: 0

A typical semiconductor is fabricated from metal and barrier layers separated by passivation layers. A further glassivation and/or polyimide layer on top of these provides environmental and mechanical protection. Optical microscopes By using optical microscopy, the semiconductor die can be inspected for failure modes such as top-down visible crack degradation, melt-down of metal conductors,... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: reactive ion etching

Gearing Up For Hybrid Bonding

Measurement Of Deep Trenches To Study The RIE Lag Effect

Demand, Lead Times Soar For 300mm Equipment

NVM Reliability Challenges And Tradeoffs

Deprocessing And SEM For Semiconductor Failure Analysis