Address Simulation Turn-Around Time Bottlenecks with VCS Fine-Grained Parallelism


Non-stop growth in design size and complexity makes it more difficult than ever for verification teams to keep up with project demands and product goals. According to the Synopsys 2017 Global User Survey, “Verification taking longer than planned” is the top reason for tapeout delays, and “Simulation runtime performance” is the top challenge for verification. Since regression test turn-a... » read more

Boosting Regression Throughput By Reusing Setup Phase Simulation


This paper discusses how to write a design so the common initial setup phase simulation is done once and then used as a foundation to run different tests later on, including the ability to change test stimulus to simulate different test behaviors. It also discusses what type of designs are appropriate for this methodology and what a designer can do to make his/her design suitable for it. Also c... » read more

Follow The Moving Money


Semiconductor economics are changing by market, by region, and by product node and packaging type, adding new complexity into decisions about which technology to use for which products and why. Money is the common denominator in all of these decisions, whether it's measured by return on invested capital, quarterly profits, or long-term investments that can include acquisitions, organic growt... » read more