Rethinking Scan Chains In Semiconductor Test


An explosion in design complexity, fueled by increased transistor density and fundamental shifts in chip architectures, are beginning to overwhelm traditional approaches to test. Defects can show up in the clock trees that drive scan chains, and even inside blocks of scan cells, which may number in the millions. Jayant D'Souza, technical product director for yield learning products in Siemens E... » read more

How To Catch “Disappearing” Latent Defects


Automotive is demanding more emphasis on chip reliability. By 2020, electronic devices will account for over 35% of the manufacturing cost of an automobile, and by 2030, that number is expected to rise to 50%. Tens of thousands of cars are manufactured each day, with each car using thousands of chips — and if even one of those chips fails in the field it may have disastrous consequences: los... » read more

The Impact Of Parameter Uncertainties On The Lifetime Prediction of Power Devices (TU Delft)


A new technical paper titled "Impact of Parameter Uncertainties on Power Electronic Device Lifetime Predictions" was published by researchers at TU Delft. Abstract "Properly addressing uncertainties in reliability analysis is essential for realistic lifetime predictions of power devices. This paper investigates parameter uncertainties on the lifetime estimation of power devices using an emp... » read more

Designing For Reliability With A System Life Estimator


From big machines to small handheld equipment, all typically come with varying warranty timelines based on estimations. If this number is overestimated or underestimated, it can incur millions of dollars in losses to manufacturers. That’s why it’s important to look at the lifetime system estimation as a bottom-up process. The efficiency in this approach results in a robust method to formula... » read more

Rethinking Chip Reliability For Harsh Conditions


As semiconductors push into environments once considered untenable, reliability expectations are being redefined. From the vacuum of space and the inside of jet engines to deep industrial automation and electrified drivetrains, chips now must endure extreme temperature swings, corrosive atmospheres, mechanical vibration, radiation, and unpredictable power cycles, all while delivering increasing... » read more

Addressing Stress In Heterogeneous 3D-IC Designs


The benefits of 3D IC architectures are well-documented – smaller footprints, lower power, and increased performance. However, the move to heterogeneous 3D designs also introduces a host of new challenges that must be carefully navigated. As chip designers integrate multiple dies and technologies into a single 3D package, the interactions between the chip and package become increasingly co... » read more

Problems In Testing AI Chips


As AI chips get larger, it becomes much harder to test them. Today, there can be as many as 22,000 pins on a 150mm² die, but in the future that number may increase to 80,000 pins. That creates a huge challenge for the fabs and the testers. Jack Lewis, chief technologist at Modus Test, talks about the intricacies of testing these complex devices, from maintaining contact with those pins even on... » read more

CFETs: Reliability of Complementary Field-Effect Transistors (TU Munich, IIT)


A technical paper titled "CFET Beyond 3 nm: SRAM Reliability under Design-Time and Run-Time Variability" was published by researchers at TU Munich and IIT Kanpur. Abstract "This work investigates the reliability of complementary field-effect transistors (CFETs) by addressing both design-time variability arising from process variations and run-time variability due to temperature and aging ef... » read more

Impact Of Cryogenic Temps On The Minimum-Operating Voltage Of 5nm FinFETs-Based SRAM (IIT, UC Berkeley et al)


A new technical paper titled "An Investigation of Minimum Supply Voltage of 5nm SRAM from 300K down to 10K" was published by researchers at Indian Institute of Technology, UC Berkeley and Munich Institute of Robotics and Machine Intelligence. Abstract "In this article, we present a comprehensive study of the impact of cryogenic temperatures on the minimum-operating voltage (Vmin) of 5 nm ... » read more

Why Thin Film Measurements Matter


Semiconductor devices are becoming thinner and more complex, making thin deposited films even harder to measure and control. With 3nm node devices in production and 2nm nodes ramping toward first-silicon, the importance of precise film measurement is only growing in significance as fabs seek to maintain the performance and reliability of leading-edge devices. Whether it’s the read and writ... » read more

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