Prediction of SRAM Reliability Under Mechanical Stress Induced by Harsh Environments


On the example of a 28nm SRAM array, this work presents a novel reliability study which takes into account the effect of externally applied mechanical stress in circuit simulations. This method is able to predict the bit failures caused by the stress via the piezoresistive effect. The stability of each single SRAM cell is simulated using static noise margin. Finally, the whole array’s behavio... » read more

Analog Reliability Analysis for Mission-Critical Applications


Rapidly increasing electrical content in automobiles is driving the need for revolution in analog integrated circuit (IC) design methodology. Compared to designing for consumer electronics, designing for mission-critical applications—industrial, medical, space, and automotive—requires a different approach to reliability analysis. We will explore how reliability analysis needs to change for ... » read more

Who’s Responsible For Transistor Aging Models?


While there are a number of ways to go about reliability and transistor aging analysis, it is all in large part dependent on fabs and foundries to provide the aging models. The situation is also not entirely clear in the semiconductor ecosystem because the classic over-the-wall mentality between design and manufacturing still exists. And unfortunately this wall is bi-directional. Not only... » read more

Transistor-Level Verification Returns


A few decades ago, all designers did transistor-level verification, but they were quite happy to say goodbye to it when standard cells provided isolation at the gate-level and libraries provided all of the detailed information required, such as timing. A few dedicated people continued to use the technology to provide those models and libraries and the most aggressive designs that wanted to stri... » read more