tag: reliability

The Critical But Less Obvious Risks In AI
By Ed Sperling - 10 Sep, 2019 - Comments: 0

AI has been the subject of intense debate since it was first introduced back in the mid-1950s, but the real threat is a lot more mundane and potentially even more serious than the fear-inducing picture painted by its critics. Replacing jobs with technology has been a controversial subject for more than a century. AI is a relative newcomer in that debate. While the term "artificial intelligen... » read more

How Hardware Can Bias AI Data
By Ed Sperling - 10 Sep, 2019 - Comments: 1

Clean data is essential to good results in AI and machine learning, but data can become biased and less accurate at multiple stages in its lifetime—from moment it is generated all the way through to when it is processed—and it can happen in ways that are not always obvious and often difficult to discern. Blatant data corruption produces erroneous results that are relatively easy to ident... » read more

IP’s Growing Impact On Yield And Reliability
By Ann Mutschler - 04 Sep, 2019 - Comments: 0

Chipmakers are finding it increasingly difficult to achieve first-pass silicon with design IP sourced internally and from different IP providers, and especially with configurable IP. Utilizing poorly qualified IP and waiting for issues to appear during the design-to-verification phase just before tape-out can pose high risks for design houses and foundries alike in terms of cost and time to... » read more

Degradation Monitoring – From Vision to Reality
By Evelyn Landman - 06 Aug, 2019 - Comments: 0

Reliability physics has historically focused on models for time-to-failure, but that approach is reaching its limit. Those models generally were developed using data gathered from very simple test structures that could be stressed to failure. Today, with electronics playing a such a critical role in our everyday life, failures are no longer an option. The underlying ICs being implemented call f... » read more

Using Better Data To Shorten Test Time
By Ed Sperling - 06 Aug, 2019 - Comments: 1

The combination of machine learning plus more sensors embedded into IC manufacturing equipment is creating new possibilities for more targeted testing and faster throughput for fabs and OSATs. The goal is to improve quality and reduce the cost of manufacturing complex chips, where time spent in manufacturing is ballooning at the most advanced nodes. As the number of transistors on a die incr... » read more

Signoff-Compatible CDC
By Ed Sperling - 29 Jul, 2019 - Comments: 2

Tanveer Singh, senior staff consulting applications engineer at Synopsys, explains why netlist clock domain crossing is now an essential complement to RTL CDC, why CDC issues are worse at advanced nodes and in AI chips, and why dealing with CDC effectively is becoming a competitive requirement for performance and low power. » read more

Material Choices In Printed Temperature Sensors
By Ed Sperling - 24 Jul, 2019 - Comments: 0

Vijaya Kayastha, lead device development engineer at Brewer Science, talks about what’s needed for printed temperature sensors, what happens when there are impurities in the materials, how these sensors respond to stress, and how costs compare to traditional sensors. » read more

Copy-Row DRAM (CROW) : Substrate for Improving DRAM
By Technical Paper Link - 22 Jun, 2019 - Comments: 0

Source/Credit: ETH Zurich & Carnegie Mellon University Click here for the technical paper and here for the power point slides » read more

Factoring Reliability Into Chip Manufacturing
By Ed Sperling - 20 Jun, 2019 - Comments: 0

Making chips that can last two decades is possible, even if it's developed at advanced process nodes and is subject to extreme environmental conditions, such as under the hood of a car or on top of a light pole. But doing that at the same price point as chips that go into consumer electronics, which are designed to last two to four years, is a massively complex challenge. Until a couple of y... » read more

Power, Reliability And Security In Packaging
By Ed Sperling - 19 Jun, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss advanced packaging with Ajay Lalwani, vice president of global manufacturing operations at eSilicon; Vic Kulkarni, vice president and chief strategist in the office of the CTO at ANSYS; Calvin Cheung, vice president of engineering at ASE; Walter Ng, vice president of business management at UMC; and Tien Shiah, senior manager for memory at Samsun... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy