tag: reliability

Changes In Scan Test Data
By Ed Sperling - 29 Jul, 2025 - Comments: 0

Bigger designs with hundred of cores are creating an explosion in the volume of scan test data, significantly bumping up the amount of time spent on test. That raises the cost of test, forcing chipmakers to trade off higher costs with reliability. The solution is to raise the level of abstraction for scan tests, using a bus and packetized data that can run at much higher frequencies than is pos... » read more

Efficient Failure-Detection Methods for GPU Control-Logic (Hitachi, Osaka Univ., Kyoto Univ.)
By Technical Paper Link - 21 Jul, 2025 - Comments: 0

A new technical paper titled "A Hardware-Aware Failure-Detection Method for GPU Control-Logic" was published by researchers at Hitachi, Ltd., Osaka University, and Kyoto University. Excerpt "Various failure detection methods have been proposed for SDCs caused by faults in data units such as registers. However, effective methods for detecting SDCs resulting from faults in control logic, such... » read more

Silent Data Corruption
By Ed Sperling - 16 Jul, 2025 - Comments: 0

Everyone expects their compute systems to generate the correct answer. When they don't, it's cause for alarm, because it's not always clear how long the problem has persisted. Even worse, chips and systems are now so complex that it may require a unique sequence of operations to trigger a silent data error, and they may show up only occasionally, and maybe only after months or years of use in t... » read more

System-Level Approach To Reducing HBM Cost for AI inference (RPI, IBM)
By Technical Paper Link - 07 Jul, 2025 - Comments: 0

A new technical paper titled "Breaking the HBM Bit Cost Barrier: Domain-Specific ECC for AI Inference Infrastructure" was published by researchers at Rensselaer Polytechnic Institute and IBM. Abstract "High-Bandwidth Memory (HBM) delivers exceptional bandwidth and energy efficiency for AI workloads, but its high cost per bit, driven in part by stringent on-die reliability requirements, pose... » read more

Rethinking Scan Chains In Semiconductor Test
By Ed Sperling - 02 Jul, 2025 - Comments: 0

An explosion in design complexity, fueled by increased transistor density and fundamental shifts in chip architectures, are beginning to overwhelm traditional approaches to test. Defects can show up in the clock trees that drive scan chains, and even inside blocks of scan cells, which may number in the millions. Jayant D'Souza, technical product director for yield learning products in Siemens E... » read more

How To Catch “Disappearing” Latent Defects
By Errol Akomer - 19 Jun, 2025 - Comments: 0

Automotive is demanding more emphasis on chip reliability. By 2020, electronic devices will account for over 35% of the manufacturing cost of an automobile, and by 2030, that number is expected to rise to 50%. Tens of thousands of cars are manufactured each day, with each car using thousands of chips — and if even one of those chips fails in the field it may have disastrous consequences: los... » read more

The Impact Of Parameter Uncertainties On The Lifetime Prediction of Power Devices (TU Delft)
By Technical Paper Link - 16 Jun, 2025 - Comments: 0

A new technical paper titled "Impact of Parameter Uncertainties on Power Electronic Device Lifetime Predictions" was published by researchers at TU Delft. Abstract "Properly addressing uncertainties in reliability analysis is essential for realistic lifetime predictions of power devices. This paper investigates parameter uncertainties on the lifetime estimation of power devices using an emp... » read more

Designing For Reliability With A System Life Estimator
By Cadence - 11 Jun, 2025 - Comments: 0

From big machines to small handheld equipment, all typically come with varying warranty timelines based on estimations. If this number is overestimated or underestimated, it can incur millions of dollars in losses to manufacturers. That’s why it’s important to look at the lifetime system estimation as a bottom-up process. The efficiency in this approach results in a robust method to formula... » read more

Rethinking Chip Reliability For Harsh Conditions
By Gregory Haley - 10 Jun, 2025 - Comments: 0

As semiconductors push into environments once considered untenable, reliability expectations are being redefined. From the vacuum of space and the inside of jet engines to deep industrial automation and electrified drivetrains, chips now must endure extreme temperature swings, corrosive atmospheres, mechanical vibration, radiation, and unpredictable power cycles, all while delivering increasing... » read more

Addressing Stress In Heterogeneous 3D-IC Designs
By Shetha Nolke - 29 May, 2025 - Comments: 0

The benefits of 3D IC architectures are well-documented – smaller footprints, lower power, and increased performance. However, the move to heterogeneous 3D designs also introduces a host of new challenges that must be carefully navigated. As chip designers integrate multiple dies and technologies into a single 3D package, the interactions between the chip and package become increasingly co... » read more

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