Power Integrity And Voltage Issues Get Harder To Detect And Solve


Voltage and power integrity are becoming increasingly critical and challenging for chip designers and architects, regardless of which process technology they are using or which market they are targeting. An explosion of features vying unevenly for current is increasing the number of constraints and possible interactions that engineers need to sort through to ensure reliability. These include... » read more

Improving IC System Quality And Performance


Ensuring that multi-die assemblies and advanced SoCs will work as expected from time zero to the end of their lifecycle adds new challenges for chipmakers and their customers. Chips are being run harder, hotter, and for longer periods of time, often in unique configurations and with customized workloads. Alex Burlak, vice president of test and analytics at proteanTecs, talks about how to identi... » read more

Ensuring Reliability Becomes Harder In Multi-Die Assemblies


Multi-die assemblies are bringing together a variety of materials and processes with distinctly different physical properties, creating significant challenges in manufacturing and packaging that can impact yield at time zero and reliability in the field. What passes electrical screening at the end of the line may look good on paper, but these devices can still fail once exposed to rapid and ... » read more

In-System Test For AI Data Centers


Testing inside the fab or packaging house can determine whether a chip or package meets all the functional requirements at time zero, but how that chip behaves in the field during its lifetime and under different workloads and environmental conditions may be very different. This is particularly true in AI data centers, where utilization of one or more dies may be significantly higher than in pr... » read more

Critical Optimization Factors For GenAI Chipmakers


Today’s GenAI arms race is fought with novel chip architectures and packaging. Specialized hardware designs are proliferating in the form of GPUs, TPUs, NPUs, and more, all tuned for parallelism and matrix-heavy AI math. In this hyper-competitive landscape, chip vendors scramble to differentiate their products on multiple fronts. They promise some mix of better performance, efficiency, or ... » read more

Unearthing Hidden Reliability Risks


Successful automotive electronic design requires a focus on safety, performance and customer satisfaction. This makes IC reliability not just a “nice to have” feature, but a fundamental requirement. From advanced driver-assistance systems (ADAS) to infotainment and powertrain controls, every IC must work with exceptional reliability, even in tough conditions. Imagine a tiny circuit flaw in ... » read more

How Multiphysics Is Powering The Future Of 3D-ICs


It’s surprising to learn that the idea of 3D integrated circuits (3D ICs) has been kicking around for over sixty years. Not long after the first MOS IC emerged in 1960, researchers were already thinking vertically. By 1983, Fujitsu manufactured the first 3D IC prototype using through-silicon via (TSV) technology, using laser beam recrystallization. That’s a long time for a good idea to catc... » read more

Silicon Lifecycle Management


How chips are used is changing, and so are the requirements. In the past, markets were largely segmented by application, which determined how chips were designed. High-performance processors went into notebook computers, low-power chipsets were deployed in mobile devices, and complex SoCs and advanced packages were used in data centers. But with the spread of AI everywhere, traditional segmenta... » read more

Navigating Reliability Potholes: Early 3D Stress Analysis For Automotive ICs


The rise of 3D integrated circuits (ICs) and heterogeneous packaging is reshaping how automotive ICs fulfill demanding analog and sensor requirements. Whether for radar, lidar, sensor fusion or domain controllers, advanced packaging enables new levels of integration—and performance—in automotive electronics. Yet, as these architectures grow more complex, they also introduce new forms of mec... » read more

Issues In Ramping Advanced Packaging


Multi-die assemblies require significantly more test data than a monolithic chip. Thermal mismatch between different layers can cause warping, which puts stress on the bonds that connect those layers, resulting in failures during testing. The big problem is that traditional daisy-chained test approaches cannot pinpoint where problems are occurring. Instead, they provide a go/no-go for the entir... » read more

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