Week In Review: Design, Low Power


Electronic system design (ESD) industry revenue is up 8.9% from $3,458.2 million in Q3 2021 to $3,767.4 million in Q3 2022 according to a report from SEMI’s ESD Alliance. Read our in-depth take on what this means. In an attempt to make a viable reusable DNA biosensor probe, NIST researchers used an extremely low-power FETdeveloped at CEA-LETI to remove noise in their DNA biosensor circuitr... » read more

CXL Picks Up Steam In Data Centers


CXL is gaining traction inside large data centers as a way of boosting utilization of different compute elements, such as memories and accelerators, while minimizing the need for additional racks of servers. But the standard is being extended and modified so quickly that it is difficult to keep up with all the changes, each of which needs to be verified and validated across a growing swath of h... » read more

The New Convergence: IoT, AI, And 5G Bring Actionable Intelligence To The Factory Floor


Last year, I reflected on the Renesas Renaissance in terms of how our long-term growth strategy is positioning the company as a full-spectrum, global technology solutions provider with an extended physical footprint in the U.S., Europe, and China. Thanks to the acquisitions of Intersil, IDT, Dialog Semiconductor, and Celeno we now have expansive design capabilities that surround our embedded... » read more

Blog Review: Jan. 25


Cadence's Shyam Sharma shares some important design and verification considerations when working with DDR5 SDRAM and DDR5 DIMM-based memory subsystems, including reset and power on initialization, speed bin compliance, and refresh, RFM, and temperature requirements. Siemens EDA's Harry Foster examines trends in adoption of languages and libraries for IC and ASIC design, testbench creation, a... » read more

Week In Review: Auto, Security, Pervasive Computing


Pervasive computing Keysight Technologies introduced its new Electrical Performance Scan (EP-Scan), a high-speed digital simulation tool for rapid signal integrity (SI) analysis for hardware engineers and printed circuit board (PCB) designers. Siemens Digital Industries Software announced the opening of its eXplore Live at The Smart Factory @ Wichita, housed at Wichita State University’... » read more

Blog Review: Jan. 18


Synopsys' Dana Neustadter, Sara Zafar Jafarzadeh, and Ruud Derwig argue that we are already at an inflection point for post-quantum security because devices and infrastructure systems with longer life cycles or communicating data that must be kept confidential for an extended period need to have a path towards quantum-safe solutions. Siemens EDA's Harry Foster looks at trends in adoption of ... » read more

Blog Review: Jan. 11


Cadence's Veena Parthan explains why in CFD, understanding the consequences of choices regarding the computational mesh is essential for generating high-fidelity simulation results. Synopsys' Chris Clark shares key considerations and questions to factor in when developing solutions for software-defined vehicles that must meet safety, security, reliability, and quality standards. Siemens E... » read more

Week In Review: Semiconductor Manufacturing, Test


TSMC is in advanced talks with key suppliers about setting up its first potential European plant in Dresden, Germany, according to Nikkei Asia. The company held a 3nm volume production and capacity expansion ceremony at its Fab 18. TSMC also is building 3nm capacity at its Arizona site, as well as opening a global R&D Center in the Hsinchu Science Park in the second quarter of 2023, to be ... » read more

Week In Review: Design, Low Power


Top Of The News Google announced it will support the RISC-V architecture with the Android open-source operating system. In a keynote at the RISC-V Summit, Lars Bergstrom, Google's director of engineering for the Android Platform Programming Languages, noted that Android currently has more than 3 billion users and the support of more than 24,000 vendors. "We've been following RISC-V for a very ... » read more

Blog Review: Jan. 4


Siemens EDA's Harry Foster investigates the percentage of total IC/ASIC project time spent in verification and increasing engineering headcount, particularly growing demand for verification engineers. Synopsys' Stelios Diamantidis argues that retargeting older chips using AI offers a way to move chip designs between nodes and absorb the market’s excess capacity. Cadence's Paul McLellan ... » read more

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