Week In Review: Manufacturing, Test

By Mark LaPedus - 14 May, 2021 - Comments: 0

Government policy Semiconductor companies as well hardware and software vendors have announced the formation of the Semiconductors in America Coalition (SIAC). The group called on congressional leaders to appropriate $50 billion for U.S. manufacturing incentives and research initiatives. SIAC’s mission is to advance federal policies that promote semiconductor manufacturing and research in th... » read more

The Week In Review: Manufacturing

By Mark LaPedus - 29 Sep, 2017 - Comments: 0

Chipmakers Who will buy Toshiba’s memory business? In the latest of what is becoming a confusing saga, Toshiba has signed a deal to sell its memory unit to a group led by Bain Capital. The Bain-led consortium will hold a 49.9% stake in the memory unit, while Toshiba will hold 40.2% and Japan’s Hoya will own 9.9%. Other members in the group include Apple, Dell, Kingston, and Seagate. In add... » read more

The Week In Review: Manufacturing

By Mark LaPedus - 15 Jul, 2016 - Comments: 0

Fab and test equipment The wafer inspection market is heating up. For example, Applied Materials announced its new e-beam inspection system for use in foundry, logic, DRAM and 3D NAND applications. In addition, KLA-Tencor introduced six wafer defect inspection and review systems for leading-edge IC device manufacturing. National Instruments has rolled out a second-generation vector sig... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.

by Ed Sperling

tag: Reno Sub-Systems

Week In Review: Manufacturing, Test

The Week In Review: Manufacturing

The Week In Review: Manufacturing