tag: RISC-V

What Interested You In 2020
By Brian Bailey - 24 Nov, 2020 - Comments: 0

In business you are always told to follow the money, but for us it is more important to follow the readership. If we are not writing what you want to read, then we are missing the mark. I like to review the ones that have garnered the most attention, in part to see if that will influence what I write about for 2021, but also to find out where the industry is looking for the most help. As Sem... » read more

Impact Of Instruction Memory On Processor PPA
By Roddy Urquhart - 24 Nov, 2020 - Comments: 0

The area of any part of a design contributes both to the silicon cost and to the power consumption. A simplistic following of the “A” in a processor IP vendor’s PPA numbers can be misleading. A processor is never in isolation but is part of a subsystem additionally including instruction memory, data memory, and peripherals. In most cases, instruction memory will be dominant and the proc... » read more

Using AI And Bugs To Find Other Bugs
By Ann Mutschler - 24 Nov, 2020 - Comments: 0

Debug is starting to be rethought and retooled as chips become more complex and more tightly integrated into packages or other systems, particularly in safety- and mission-critical applications where life expectancy is significantly longer. Today, the predominant bug-finding approaches use the ubiquitous constrained random/coverage driven verification technology, or formal verification techn... » read more

RISC-V Custom Instruction Flow Application Note
By Imperas - 23 Nov, 2020 - Comments: 0

A RISC-V processor has several defined decode spaces, for example custom0, custom1 etc. into which new custom instructions can be added. OVP Fast processor models can be extended without modification to the pre-compiled and verified base processor model source code using one or more extension libraries. An extension library can be loaded as part of a virtual platform definition in addition to t... » read more

Speeding Up AI With Vector Instructions
By Ann Mutschler - 04 Nov, 2020 - Comments: 0

A search is underway across the industry to find the best way to speed up machine learning applications, and optimizing hardware for vector instructions is gaining traction as a key element in that effort. Vector instructions are a class of instructions that enable parallel processing of data sets. An entire array of integers or floating point numbers is processed in a single operation, elim... » read more

Is Hardware-Assisted Verification Avoidable?
By Brian Bailey - 29 Oct, 2020 - Comments: 1

Emulation is emerging as the tool of choice for complex and large designs, but companies that swap from simulation to emulation increasingly recognize this is not an easy transition. It requires money, time, and effort, and even then not everyone gets it right. Still, there are significant benefits to moving from simulation to emulation, providing these systems can be utilized efficiently en... » read more

Blog Review: Oct. 7
By Jesse Allen - 07 Oct, 2020 - Comments: 0

In a blog for Arm, University of Southampton PhD student Sivert Sliper looks at how energy-driven and intermittent computing could be used to power trillions of IoT devices and introduces a SystemC-based simulator for such systems. Mentor's Chris Spear explains why transaction classes should extend from uvm_sequence_item rather than uvm_transaction when designing UVM testbenches. Cadence'... » read more

RISC-V: Will There Be Other Open-Source Cores?
By Ed Sperling - 06 Oct, 2020 - Comments: 5

Part 3: Semiconductor Engineering sat down to discuss the business and technology landscape for RISC-V with Zdenek Prikryl, CTO of Codasip; Helena Handschuh, a Rambus Security Technologies fellow; Louie De Luna, director of marketing at Aldec; Shubhodeep Roy Choudhury, CEO of Valtrix Systems; and Bipul Talukdar, North America director of applications engineering at SmartDV. What follows are exc... » read more

Defining Processor Core Complexity
By Roddy Urquhart - 24 Sep, 2020 - Comments: 0

The more complex a processor core, the larger the area and power consumption. But increasing complexity is not a single dimension, as processors can be more complex in different ways. In selecting a processor IP core, it is important to choose the right sort of complexity for your project. Some ways of thinking about complexity include: Word length Execution units Privilege/prot... » read more

Creating Domain-Specific Processors Using Custom RISC-V ISA Instructions
By Codasip - 23 Sep, 2020 - Comments: 0

When System-on-Chip (SoC) developers include processors in their designs, they face choices in solving their computational challenges. Complex SoCs will usually have a variety of processor cores responsible for varied functions such as running the main application programs, communications, signal processing, security, and managing storage. Traditionally, such cores have been in distinct categor... » read more

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