A Path To Increase Cell Utilization Rate And Decrease Routing Congestion In Chip Design Floorplanning

By Jim Schultz - 30 Nov, 2023 - Comments: 0

What do chip floorplanning and city planning have in common? As it turns out, quite a lot. This was the premise for an award-winning talk given by MediaTek at this year’s Synopsys User Group (SNUG) in Taiwan. Urban city development was used as an example to understand how utilization rate (UR) and congestion relate to chip planning. UR was defined in the example as population density while... » read more

ML-based Routing Congestion And Delay Estimation In Vivado ML Edition

By Xilinx - 03 Nov, 2021 - Comments: 0

The FPGA physical design flow offers a compelling opportunity for Machine Learning for CAD (MLCAD) for the following reasons: • An ML solution can be applied wholesale to a device family. • There is a vast data farm that can be harvested from device models and design data from broad applications. • There is a single streamlined design flow that an be instrumented, annotated, and quer... » read more

Unified Compression and LBIST in a Physically Aware Environment

By Cadence - 27 Feb, 2019 - Comments: 0

Unified compression is a new approach that unifies scan compression and logic built-in self-test (LBIST). It leverages recent innovations from Cadence in physically-aware design for test (DFT) to solve routing congestion and area issues from traditional discrete approaches and delivers a confident path to high-quality test. On a sample design, area savings of 35–47%, and scan wirelength savin... » read more

Dealing With New Bottlenecks

By Ed Sperling - 11 Jul, 2013 - Comments: 0

By Ed Sperling While the number of options for improving efficiency and performance in designs continues to increase, the number of challenges in getting chips at advanced process nodes out the door is increasing, too. Thinner wires, routing congestion, more power domains, IP integration and lithography issues are conspiring to make design much more difficult than in the past. So why aren�... » read more

Design Topology Requires Physical Data

By Ann Mutschler - 25 Apr, 2013 - Comments: 0

By Ann Steffora Mutschler To best understand a design topology and make decisions on clock/register gating, vector sets are required for the RTL tools to understand how to gate clocks and registers. However, if certain constraints are set on all enabled signals in RTL they can be re-used for gating clocks and registers downstream where enablers are not available—even without needing a ... » read more

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tag: routing congestion

A Path To Increase Cell Utilization Rate And Decrease Routing Congestion In Chip Design Floorplanning

ML-based Routing Congestion And Delay Estimation In Vivado ML Edition

Unified Compression and LBIST in a Physically Aware Environment

Dealing With New Bottlenecks

Design Topology Requires Physical Data

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