tag: rowhammer

Rowhammer Vulnerability Of A HBM2 DRAM Chip
By Technical Paper Link - 01 Jun, 2023 - Comments: 0

A new technical paper titled "An Experimental Analysis of RowHammer in HBM2 DRAM Chips" was published by researchers at ETH Zurich and American University of Beirut. Abstract: "RowHammer (RH) is a significant and worsening security, safety, and reliability issue of modern DRAM chips that can be exploited to break memory isolation. Therefore, it is important to understand real DRAM chips' ... » read more

State of the Art And Future Directions of Rowhammer (ETH Zurich)
By Technical Paper Link - 18 Apr, 2023 - Comments: 0

A new technical paper titled "Fundamentally Understanding and Solving RowHammer" was published by researchers at ETH Zurich. Abstract "We provide an overview of recent developments and future directions in the RowHammer vulnerability that plagues modern DRAM (Dynamic Random Memory Access) chips, which are used in almost all computing systems as main memory. RowHammer is the phenomenon in... » read more

How To Safeguard Memory Interfaces By Design
By Dana Neustadter - 06 Apr, 2023 - Comments: 0

By Dana Neustadter and Brett Murdock In 2017, the credit bureau Equifax announced that hackers had breached its system, unleashing the personal information of 147-million people. As a result, the company has settled a class action suit for $425 million to aid those impacted, including identity theft, fraud, financial losses, and the expenses to clean up the damage. Whether the threat is iden... » read more

Week In Review: Design, Low Power
By Marie C. Baca - 22 Dec, 2022 - Comments: 0

RISC-V The European Union said it will spend the equivalent of $286.5 million on a high performance computing ecosystem based on RISC-V. According to the call for proposals, the aim of the project is to “establish a partnership between the EuroHPC JU and a consortium of industry, research organizations and institutions in HPC to the development of innovative HPC hardware and software technol... » read more

Rowhammer Mitigation: In-DRAM Mechanism Scaling The Number of Refreshes With Activations (ETH Zurich)
By Technical Paper Link - 20 Dec, 2022 - Comments: 0

A technical paper titled "REGA: Scalable Rowhammer Mitigation with Refresh-Generating Activations" was written by researchers at Computer Security Group (COMSEC), ETH Zurich and Zentel Japan. The paper will be presented at IEEE's Symposium on Security and Privacy in May 2023. "With REGA, we propose the first fully in-DRAM mitigation capable of protecting devices independently from their blas... » read more

Rowhammer: Recent Developments & Future Directions (ETH Zurich)
By Technical Paper Link - 20 Nov, 2022 - Comments: 0

A new technical paper titled "Fundamentally Understanding and Solving RowHammer" was published by researchers at ETH Zurich. Abstract: "We provide an overview of recent developments and future directions in the RowHammer vulnerability that plagues modern DRAM (Dynamic Random Memory Access) chips, which are used in almost all computing systems as main memory. RowHammer is the phenomenon i... » read more

Memory-Based Cyberattacks Become More Complex, Difficult To Detect
By John Koon - 03 Nov, 2022 - Comments: 0

Memories are becoming entry points for cyber attacks, raising concerns about system-level security because memories are nearly ubiquitous in electronics and breaches are difficult to detect. There is no end in sight with hackers taking aim at almost every consumer, industrial, and commercial segment, and a growing number of those devices connected to the internet and to each other. According... » read more

Decreasing Refresh Latency of Off-the-Shelf DRAM Chips
By Technical Paper Link - 28 Sep, 2022 - Comments: 0

A new technical paper titled "HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips" was published by researchers at ETH Zürich, TOBB University of Economics and Technology and Galicia Supercomputing Center (CESGA). Abstract "DRAM is the building block of modern main memory systems. DRAM cells must be periodically refreshed to prevent data loss. Refresh oper... » read more

Setting The Memory Controller Free From Managing DRAM Maintenance Ops (ETH Zurich)
By Technical Paper Link - 14 Sep, 2022 - Comments: 0

A new technical paper titled "A Case for Self-Managing DRAM Chips: Improving Performance, Efficiency, Reliability, and Security via Autonomous in-DRAM Maintenance Operations" was published by researchers at ETH Zurich. Abstract: "The rigid interface of current DRAM chips places the memory controller completely in charge of DRAM control. Even DRAM maintenance operations, which are used to en... » read more

An Escalation of Rowhammer To Rows Beyond Immediate Neighbors
By Technical Paper Link - 15 Aug, 2022 - Comments: 0

Researchers at Graz University of Technology, Lamarr Security Research, Google, AWS, and Rivos presented this new technical paper titled "Half-Double: Hammering From the Next Row Over" at the USENIX Security Symposium in Boston in August 2022. Abstract: "Rowhammer is a vulnerability in modern DRAM where repeated accesses to one row (the aggressor) give off electrical disturbance whose cumu... » read more

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