Achieving Faster Closure With Reduced Setup And Debug Using Advanced RTL Static Signoff Platform

By Synopsys - 03 Mar, 2021 - Comments: 0

Many design houses are continually seeking ways to shorten their effective design cycle to address demanding market requirements, gain a formidable technological advantage, and secure leadership in their respective industries. This pressure can cause designers to get extremely overwhelmed by strict timelines. To meet tight project timelines, design teams often resort to identifying industry-lea... » read more

Better Quality RTL

By Ann Mutschler - 02 Feb, 2021 - Comments: 0

How do you measure the quality of RTL? Philippe Luc, director of verification at Codasip, talks about identifying bugs, improving the overall quality of the verification, what happens when different blocks are used in a design, and how to improve efficiency in the verification process. » read more

An Automated Pre-Silicon IP Trustworthiness Assessment For Hardware Assurance

By OneSpin Solutions - 27 Jan, 2021 - Comments: 0

Paper presented by Sergio Marchese & John Hallman of OneSpin Solutions & The Aerospace Corporation. Integrated circuit designs include in-house and third-party intellectual properties that could contain hardware Trojans. An independent, trusted, and complete IP model, suitable for automated formal comparison with the IP register-transfer level (RTL) code using commercially available ... » read more

Shift Left Verification With Comprehensive Lint Signoff

By Synopsys - 08 Jul, 2020 - Comments: 0

With soaring complexity and continuously increasing chip sizes, achieving efficient and predictable design closure has become a prominent challenge among designers today. Demand for a faster time to market is forcing designers to find ways to shorten design cycles with accurate, efficient, one-time RTL to silicon. To meet these requirements designers are looking to implement early ”shift left... » read more

RTL Architect: Simply Better RTL

By Synopsys - 27 May, 2020 - Comments: 0

Electronic devices play a key role in society. They connect us to one another through voice, video and chat. They entertain, educate, protect and heal us in new and ever-expanding ways. They have changed the way we work, live and play. Silicon chips are the fast beating heart (2 to 3 billion beats per second) of these devices. For decades, the relentless advancements in semiconductor process te... » read more

Fusion Technology

By Synopsys - 22 Apr, 2020 - Comments: 0

Learn how the recent semiconductor industry shifts are breaking the traditional RTL-to-GDSII flow, and how the new Synopsys Fusion Technology helps you cross the chasm. To read more, click here. » read more

Building A Safety Verification Flow

By Ed Sperling - 24 Mar, 2020 - Comments: 0

Sal Alvarez, senior manager of application engineering at Synopsys, explains how safety verification differs from functional verification, what changes with failure mode effects analysis, and how to determine and verify the effectiveness of safety features. » read more

Timing Closure At 7/5nm

By Ed Sperling - 17 Mar, 2020 - Comments: 2

Mansour Amirfathi, director of application engineering at Synopsys, examines how to determine if assumptions about design are correct, how many cycles are needed for a particular operation and why this is so complicated, and what happens if signals get out of phase. » read more

Power Management Becomes Top Issue Everywhere

By Ann Mutschler - 12 Mar, 2020 - Comments: 1

Power management is becoming a bigger challenge across a wide variety of applications, from consumer products such as televisions and set-top-boxes to large data centers, where the cost of cooling server racks to offset the impact of thermal dissipation can be enormous. Several years ago, low-power design was largely relegated to mobile devices that were dependent on a battery. Since then, i... » read more

Reducing Power At RTL

By Ann Mutschler - 13 Feb, 2020 - Comments: 0

Power management and reduction at the register transfer level is becoming more problematic as more heterogeneous elements are added into advanced designs and more components are dependent on interactions with other components. This has been a growing problem in leading-edge designs for the past couple of process nodes, but similar issues have begun creeping into less-sophisticated designs as... » read more

← Older posts Newer posts →

Knowledge Centers
Entities, people and technologies explored

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: RTL

Achieving Faster Closure With Reduced Setup And Debug Using Advanced RTL Static Signoff Platform

Better Quality RTL

An Automated Pre-Silicon IP Trustworthiness Assessment For Hardware Assurance

Shift Left Verification With Comprehensive Lint Signoff

RTL Architect: Simply Better RTL

Fusion Technology

Building A Safety Verification Flow

Timing Closure At 7/5nm

Power Management Becomes Top Issue Everywhere

Reducing Power At RTL

Trending Articles

Hybrid Bonding Makes Strides Toward Manufacturability

Americas Chip Funding Energizes Industry

Advanced Packaging Driving New Collaboration Across Supply Chain

Startup Funding: Q3 2024

Chiplets Make Progress Using Interconnects As Glue

Knowledge Centers
Entities, people and technologies explored