How To Optimize Verification

By Brian Bailey - 25 Jul, 2019 - Comments: 0

The rate of improvement in verification tools and methodologies has been nothing short of staggering, but that has created new kinds of problems for verification teams. Over the past 20 years, verification has transformed from a single language (Verilog) and tool (simulator) to utilizing many languages (testbench languages, assertion languages, coverage languages, constraint languages), many... » read more

Week In Review: Manufacturing, Test

By Mark LaPedus - 19 Jul, 2019 - Comments: 0

Chipmakers TSMC posted mixed results for the second quarter. It also presented a mixed outlook for the third quarter, according to various reports. TSMC and Samsung are in the midst of a foundry battle at 7nm and 5nm. “TSMC raised its 2019 capex outlook to over $11B, up from prior guidance of $10B-$11B. The increased capex is to support 5nm and 7nm ramps, with accelerated 5G investment a... » read more

200mm Cools Off, But Not For Long

By Mark LaPedus - 18 Jul, 2019 - Comments: 4

After years of acute shortages, 200mm fab capacity is finally loosening up, but the supply/demand picture could soon change with several challenges on the horizon. 200mm fabs are older facilities with more mature processes, although they still churn out a multitude of today’s critical chips, such as analog, MEMS, RF and others. From 2016 to 2018, booming demand for these and other chips ca... » read more

Challenges Grow For 5G Packages And Modules

By Mark LaPedus - 18 Jul, 2019 - Comments: 0

The shift to 5G wireless networks is driving a need for new IC packages and modules in smartphones and other systems, but this move is turning out to be harder than it looks. For one thing, the IC packages and RF modules for 5G phones are more complex and expensive than today's devices, and that gap will grow significantly in the second phase of 5G. In addition, 5G devices will require an as... » read more

Week In Review: Design, Low Power

By Jesse Allen - 05 Jul, 2019 - Comments: 0

Si2's Unified Power Model has been approved as IEEE 2416-2019, a new Standard for Power Modeling to Enable System Level Analysis, which complements UPF/IEEE 1801-2018. UPM/IEEE 2416-2019 provides a set of power modeling semantics enabling system designers to model entire systems with flexibility. It supports power modeling from abstract design description to gate level implementation, providing... » read more

Applied Buys Kokusai For $2.2B

By Mark LaPedus - 01 Jul, 2019 - Comments: 0

Applied Materials has signed a definitive agreement to acquire Kokusai Electric for $2.2 billion in cash from investment firm KKR. For years, Kokusai Electric was a subsidiary of Hitachi. It sells epitaxial, thermal processing and other equipment. Then, as part of a complex business deal, KKR in 2017 acquired the semiconductor equipment business of Hitachi Kokusai Electric from Hitachi. ... » read more

Week In Review: Manufacturing, Test

By Mark LaPedus - 28 Jun, 2019 - Comments: 0

Market research What’s the CapEx outlook for 2020? Semiconductor capital spending is down in 2019, but the industry faces another slump in 2020, according to IC Insights. The firm sees a 15% decline in CapEx for 2019 with a 5% drop expected in 2020. New 300mm fab construction in Korea is still going strong despite the memory downturn, according to SEMI. “Korea’s fab construction spen... » read more

Manufacturing Bits: June 25

By Mark LaPedus - 25 Jun, 2019 - Comments: 0

Panel-level consortium Fraunhofer is moving forward with the next phase of its consortium to develop technologies for panel-level packaging. In 2016, Fraunhofer launched the original effort, dubbed the Panel Level Packaging Consortium. The consortium, which had 17 partners, developed various equipment and materials in the arena. Several test layouts were designed for process development on ... » read more

5nm Vs. 3nm

By Mark LaPedus - 24 Jun, 2019 - Comments: 16

Foundry vendors are readying the next wave of advanced processes, but their customers will face a myriad of confusing options—including whether to develop chips at 5nm, wait until 3nm, or opt for something in between. The path to 5nm is well-defined compared with 3nm. After that, the landscape becomes more convoluted because foundries are adding half-node processes to the mix, such as 6nm ... » read more

What’s Next In Advanced Packaging

By Mark LaPedus - 20 Jun, 2019 - Comments: 3

Packaging houses are readying the next wave of advanced IC packages, hoping to gain a bigger foothold in the race to develop next-generation chip designs. At a recent event, ASE, Leti/STMicroelectronics, TSMC and others described some of their new and advanced IC packaging technologies, which involve various product categories, such as 2.5D, 3D and fan-out. Some new packaging technologies ar... » read more

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eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

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Megafabs churning out the most advanced processors are not the only game in town.

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tag: Samsung

How To Optimize Verification

Week In Review: Manufacturing, Test

200mm Cools Off, But Not For Long

Challenges Grow For 5G Packages And Modules

Week In Review: Design, Low Power

Applied Buys Kokusai For $2.2B

Week In Review: Manufacturing, Test

Manufacturing Bits: June 25

5nm Vs. 3nm

What’s Next In Advanced Packaging