New Technologies To Support 3D-ICs

Experts at the Table: 3D design and packaging is creating new demand on tools and requires a tight ecosystem and sharing across the industry.


Semiconductor Engineering sat down to discuss changes required throughout the ecosystem to support three-dimensional (3D) chip design with Norman Chang, chief technologist for the Semiconductor Business Unit of ANSYS; John Park, product management director for IC packaging and cross-platform solutions at Cadence; John Ferguson, director of marketing for DRC applications at Mentor, a Siemens Business; Kevin Yee, foundry director for Samsung Semiconductor; and Bapi Vinnakota, director for silicon architecture program management at Netronome, and Open Domain-Specific Architecture (ODSA) subproject lead for Open Compute Project (OCP). What follows are excerpts of that conversation. Part one of this discussion can be found here.

SE: Is the slowdown in Moore’s Law driving the migration to 3D?

Yee: It is the same story — how do we sustain Moore’s Law, and 3D is the alternative to transistors scaling. So it is anyone who was looking at big dies in the past. They are the ones driving this. We want more transistors and we just cannot scale anymore, so 3D gives us the alternative to sustain Moore’s Law and to get bigger in the same amount of area.

Park: That would apply to commercial, but not so much to DoD. That is a different story and where chiplets come into play.

Yee: But even in chiplets, if you look at the workloads for AI, ML, accelerators, are they doing the same thing?

Chang: How about CMOS image sensor? Is that 2.5D or 3D?

Park: That is a full 3D stack.

Ferguson: It is interesting that 2½ years ago 2.5D came on board, and now it is in full-blown production everywhere. But we had two options — there were silicon or organic interposers. Now we can say things are going crazy again, just like 2½ years ago, but we have maybe five different ways of doing stacks and I don’t think it is going to coalesce. I don’t think it will be one or two that survive. Each one is driven by unique requirements for a specific domain and they are different across all of them. So we will have to support five or six approaches, and that will be a challenge.

Park: It is all because of Moore’s law coming to an end. It doesn’t matter if it happened at 28nm or at 2nm.

Yee: We have been saying that for a long time.

Park: But that is why packaging has become such a big thing.

SE: There is a lot of new technology required to get to 3D, but it doesn’t appear that a lot of it is coming from academia. Does this create a different dynamic?

Park: There are some people in academia and in the DoD that are experimenting with this technology. They may not be fully sharing that with the commercial markets yet. But in spaces like AI/ML, there are things that come into play that are not just about gluing things together and routing between them. It is a dramatic change in everything about packaging. It is the tools that you use, it is the expertise that you need. There are people today who are de-aggregating SoCs. ‘I can’t design at 7nm because it costs too much, and I am only going to ship 10,000 units so I will never recoup the NRE.’ So they want a modularized approach, and I know companies that do not hire ASIC designers anymore. They hire board designers because it becomes a problem that looks more like a PCB, where you are placing discrete components that work off different protocols and communications interfaces. ‘How do I hook those up and how do I get the timing right?’ It impacts tools, flows and the expertise needed, and all of this stuff seems to be happening all at once.

Yee: We are a foundry and packing is a very big focus for us, for both 2.5D and 3D. Five or 10 years ago, you had OSATs and outside packaging to handle everything, but now that is a major focus for the foundry because we have to do that for our customers. It is not just about wafers. It is about the packaging and how it all interacts.

Park: That is an important point because it is not just Samsung. It is TSMC and it is Intel.

Yee: You are seeing the ecosystem change because of this.

SE: Will this relationship evolve over time? I am not aware of any foundry today that would take dies from another foundry and do the packaging. Do we have to figure out new rules of engagement for this?

Yee: I wouldn’t say that we wouldn’t, but the environment is changing about how to do that. In the same way that Cadence and Mentor work together because the tools flows have to work together, we are not arrogant enough to believe that everything has to be us. You have to support the customers and what they want.

Chang: How does the foundry work with the OSAT?

Yee: We have to work closely with the OSATs, as well, the same way as the other foundries do. We make sure that the flows are in place.

Chang: But you are not getting revenues from them.

Yee: It is a partnership, an ecosystem, and this is the way that the industry works.

SE: Is there a relationship building between the tool provider and customers, where the customer asks for specific technical challenges to be overcome and then the tool vendors work out how to do that?

Park: It is at two levels. One is that the foundries now do packaging, and this is a great thing for the industry because it drives reference flows. When the OSATs were doing packing there were no reference flows, there were no PDKs, you had to guess everything. Now foundries are doing it and we have reference flows. So we work with the foundries to develop certified reference flows. That is one level — do you have the baseline capability to do Samsung packaging type A? Yes. Here are the flow and the tools. But then we go out and talk to a customer who says, ‘I need more than that. I need route resource sharing.’ That is what EDA is about. We do automation. It is about taking the technology that we have and modifying it. It used to be easy. If you look at InFO — fan-out wafer level packaging technology from TSMC – that was a minor change. We were able to take the tools and make minor adjustments to the flow and get that to work. 3D is not that. It is dramatically different across the whole flow. We cannot take a route engine that worked for a single chip and have it route three chips in a stack. That takes a lot of new code. We work with the customers and partners to figure out a baseline for the reference flows and then what the advanced customers need. It is an ecosystem.

Yee: With 3D, we have to work with the partners because things change. You talk about die bonding and alignment and TSVs, and the EDA companies cannot do it on their own because it impacts how you do the process and everything. So you have to build an ecosystem. Customers will come out with new ideas about what they want.

Ferguson: They drive it and somehow we find a solution.

SE: Presumably it is an iterative process. You hit problems and work on that and then move onto something else.

Yee: Yes and no. Customer expect us to anticipate the problems. They don’t want to be the first ones to find it. That is why the collaboration becomes so important. We share ideas and issues. The customer does not want to be the pipe cleaner.

Ferguson: There are scenarios where we all go through something that we thought would work and it doesn’t. They didn’t want to be the pipe cleaner but you were – sorry.

SE: Yield has been mentioned a couple of times. One says yield will go down with 3D, and the other says yield will go up. We learned with memory that if you build a big enough memory it will fail, so you add redundancy. How do we apply those ideas to 3D stacks?

Ferguson: Even with HBM, they continue to try to shrink all of the components and they are finding that they are having stress problems. They are coming back and saying, ‘We need more help. We need to be told where and why we have these stress issues when I have smaller and smaller TSVs and more of them. How far can I push the limit?’ All of this is constant change, continuous learning. Everyone wants to be at the head of the curve but not take the risk of being at the head of the curve. So we all share that pain equally.

Park: It goes back to the known-good-die issue. That is what has plagued the multi-chip market, and now it has become more complex because you have these extra stress issues. We used to just stick things side by side on something fairly solid, and now we are taking two thin things and sticking them directly together. So the test technology has to be improved. Within EDA, we feel confident that the work we have done for testing is there. It doesn’t mean that there will be no failures, but at least you know something is bad and to throw it away.

Ferguson: If you follow the protocol.

Chang: This is always the argument of the known good die. How much testing do you do before you will put good dies together. That is the preferred methodology.

Ferguson: It comes down to the price of those chips.

Chang: Exactly.

Ferguson: How much can you afford?

Yee: One part is known good die, but the other is that once you have bonded something, if you have a yield issue from there, it can cascade. This is one of the most important things to end customers — yield. We are incentivized to make sure we work with our EDA partners, because the better the testing, the happier the customers. And for the fab, it is about yield. So testing is very important, and the first part is known good die. The second part is how do we test after you have multi-die, be it failures in the bonding process, failures in the alignment process, etc.

Vinnakota: There is an upside to this. 3D requires a number of extra interfaces. It could be silly things like loop-back tests — anything to make sure the interfaces work, to cleanly put that into the scan chain. With the new interfaces, they give you new observations points inside the package that were not there before. The trick is that everyone has to agree on a standard way of operating, managing and accessing those interfaces. Even if you have different ways for the chips to talk to each other, if you can all agree on one standard way for accessing and managing these interfaces then it makes the test problem marginally easier because you can access everything from outside of the chip. So you can even have one chip trigger a self-test of another chip. But there is no standard way to access these internals, and that is an opportunity.

Ferguson: There is the compounded issue that now you need more and more tests because you have more stuff, but that is the same as Moore’s Law has always been — more failure mechanisms. Do you really have all the right tests to find the new failure mechanisms? That is a new question. We think we do, but we keep going with that assumption until we find out that we are wrong, and then we will find a new way to test for that problem.

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