tag: scan test

Speeding Up Scan-Based Volume Diagnosis
By Bryon Moyer - 07 Dec, 2021 - Comments: 0

In the critical process known as new-product bring-up, it’s a race to get new products to yield as quickly as possible. But the interplay between increasingly complex aspects of designs and process makes it difficult to find root causes of yield issues so they can be fixed quickly. Advanced processes have very high defectivity, and learning must be fast and effective. While progress has be... » read more

Novel Reversible Chain Diagnosis Improves Resolution
By Jayant D'Souza - 09 Nov, 2021 - Comments: 0

Yield ramp for ICs designed on advanced process technologies faces new challenges because of the very complicated silicon defect types and defect distribution. Yield ramp and yield improvement are not just about profitability and time-to-market, but also have a role in today’s electronics supply chain crisis. That means yield ramp affects not just the IC maker, but the global economy. Ever... » read more

The Era Of Packetized Scan Test Has Arrived
By Geir Eide - 07 Sep, 2021 - Comments: 0

For decades, process and design scaling has triggered the adoption of transformative test solutions. About twenty years ago, when at-speed test became a de-facto requirement, on-chip compression became the norm to address test data time and volume. Over the last decade, hierarchical DFT enabled DFT engineers to apply a divide and conquer on large design, improving both implementation effort and... » read more

High-Quality Test And Embedded Analytics Are Vital For Secure SoCs
By Lee Harrison - 02 Sep, 2021 - Comments: 0

Applications such as smart cards and devices used in the defense industry require security features to ensure that sensitive data is inaccessible to outside agents. This used to be a niche requirement met through custom solutions. However, now that automotive and cyber-physical systems are proliferating, the requirements around secure test and monitoring are becoming mainstream. The current bes... » read more

Packetized Scan Test Delivery
By Geir Eide - 06 Jul, 2021 - Comments: 0

The traditional approach to moving scan test data from chip-level pins to core-level scan channels is under pressure due to the dramatic rise in design size, design complexity, and test adaptation. To address these challenges, we now have the option of implementing a packetized data network for scan test that moves the scan data through the SoC much more efficiently than the traditional pin-... » read more

Have It All With No-Compromise DFT
By Geir Eide - 28 Jan, 2021 - Comments: 0

The dramatic rise in manufacturing test time for today’s large and complex SoCs is rooted in the use of traditional approaches to moving scan test data from chip-level pins to core-level scan channels. The pin-multiplexing (mux) approach works fine for smaller designs but can become problematic with an increase in the number of cores and the design complexity on today’s SoCs. The next revol... » read more

Digital Test Bulks Up – Or Down
By Bryon Moyer - 08 Dec, 2020 - Comments: 2

Large digital integrated circuits are becoming harder to test in a time- and cost-efficient manner. AI chips, in particular, have tiled architectures that are putting pressure on older testing strategies due to the volume of test vectors required. In some cases, these chips are so large that they exceed reticle size, requiring them to be stitched together. New testing efficiencies are needed... » read more

Making IC Test Faster And More Accessible: Part 2
By Randy Fish - 11 Nov, 2020 - Comments: 0

Recently, my colleague Robert Ruiz described a new approach to scan test that utilizes the high-speed I/O (HSIO) ports that exist on most chips. The benefits of this new approach include reduced test time and cost thanks to the high-speed interface. Simplified pin electronics and tester setup are also benefits, as is the ability to run manufacturing tests in the field in support of silicon life... » read more

Making IC Test Faster And More Accessible: Part 1
By Robert Ruiz - 30 Oct, 2020 - Comments: 0

The fundamental challenges of IC test have been the same for a long time. At the heart of all test strategies is controllability and observability. First, control the state of the chip with known test vectors and then observe the chip to determine if it exhibits good or faulty behavior. There have been many innovations over the years to make the required testing of chips more tractable. Thanks ... » read more

Scan Diagnosis
By Ed Sperling - 20 Dec, 2019 - Comments: 1

Jayant D’Souza, product manager at Mentor, a Siemens Business, explains the difference between scan test and scan diagnosis, what causes values in a scan test to change, how this can be used to hone in on the actual cause of a failure in a design, and how to utilize test hardware more efficiently. » read more

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