Week In Review: Manufacturing, Test


Chipmakers, OEMs Reports have surfaced that TSMC has delayed its 3nm process. But TSMC says the technology remains on track. Volume production for TSMC’s 3nm is still scheduled for the second half of 2022. On the flip side, there is speculation that TSMC may increase its wafer prices by up to 20%, according to a report from the Taipei Times. Here's another report. This is due to chip shortag... » read more

Blog Review: Aug. 25


Arm's Fernando Garcia Redondo, Pranay Prabhat, and Mudit Bhargava introduce an open source framework and compact model for the simulation, characterization, and analysis of MRAM magnetic tunnel junctions. Siemens EDA's Chris Spear continues the tutorial on SystemVerilog class variables with a look at how to use the $cast() system task to copy between base and derived class variables. Syno... » read more

Week In Review: Manufacturing, Test


Chipmakers, OEMs At Intel’s Architecture Day this week, the company revealed several new chip architectures. Some were already announced, while others are new. These include Intel’s first performance hybrid architecture, a data center architecture, a discrete gaming graphics processing unit (GPU) architecture, infrastructure processing units (IPUs), and a data center GPU architecture. Here... » read more

Week In Review: Auto, Security, Pervasive Computing


Security Infineon Technologies is coordinating a group of twelve partners, including researchers, electronics industry, and end users, who are working to find and fix IoT security flaws. The research project, called “Design methods and hardware/software co-verification for the unique identifiability of electronic components” falls under VE-VIDES, which is part of the Trustworthy Electronic... » read more

Blog Review: Aug. 18


Arm's Charlotte Christopherson explores the possibilities of flexible, non-silicon electronics with the creation of PlasticArm, an ultra-minimalist Cortex-M0-based SoC that, even with just 128 bytes of RAM and 456 bytes of ROM, is twelve times more complex than previous flexible electronics. Cadence's Claire Ying highlights the importance of integrity and data encryption (IDE) technology for... » read more

Week In Review: Auto, Security, Pervasive Computing


Automotive Infineon announced a new MEMS scanner chipset for automotive heads-up displays (HUD) and AR (augmented reality) eyeglasses. The design has MEMS mirror — which tilts and can work with laser beam scanner (LBS) projectors — and MEMS driver. The size and energy use is small and yet it projects content over a wider area of the windshield. A partnership between Ansys and IPG Automo... » read more

Blog Review: Aug. 11


Arm's Rahul Mathur finds that traditional interconnects have become a bottleneck for improving IC performance and suggests buried interconnects as a way to lower signal routing delay. Cadence's Paul McLellan checks out forksheet FETs, a new transistor type that could allow scaling past 3nm, and the interconnect advances that will need to accompany it. A Synopsys writer explains the new LP... » read more

Blog Review: Aug. 4


Cadence's Paul McLellan listens in as industry luminaries celebrate 50 years of the microprocessor with a discussion on major challenges to the growth of microprocessors, inflection points over the last 50 years, and predictions for the next 25. Siemens EDA's Vladimir Kirichenko warns that designing electrical and thermal systems separately may lead to various problems such as late design ch... » read more

Week In Review: Manufacturing, Test


Chipmakers Intel has outlined its new process technology roadmap with plans to regain the leadership position in the market. As part of the move, Intel has changed the way it designates the nodes, revealed its new gate-all-around (GAA) transistor, and disclosed a customer for the GAA technology--Qualcomm. And not to be outdone, Intel has broadened its packaging portfolio. Intel is changing ... » read more

Week In Review: Auto, Security, Pervasive Computing


Automotive SGS-TÜV Saar certified that Cadence’s Tensilica Xtensa processors with FlexLock meets the ISO 26262:2018 standard to ASIL-D level. The new FlexLock feature is key to the certification because it supports lockstep, a fault-tolerant method that runs the same operation on two cores at the same time and then compares the output. Any difference in the output can be examined for issues... » read more

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