Dynamically Reconfiguring Logic

By Ed Sperling - 12 Jul, 2021 - Comments: 0

Dynamic reconfiguration of semiconductor logic has been possible for years, but it never caught on commercially. Cheng Wang, co-founder and senior vice president of software and engineering at Flex Logix, explains why this capability has been so difficult to utilize, what’s changed, how a soft logic layer can be used to control when to read, compute, steer, and write data back to memory, and ... » read more

Steep Spike For Chip Complexity And Unknowns

By Ed Sperling - 05 May, 2021 - Comments: 0

Cramming more and different kinds of processors and memories onto a die or into a package is causing the number of unknowns and the complexity of those designs to skyrocket. There are good reasons for combining all of these different devices into an SoC or advanced package. They increase functionality and can offer big improvements in performance and power that are no longer available just b... » read more

Next-Gen Design Challenges

By Ed Sperling - 20 Apr, 2021 - Comments: 0

As more heterogeneous chips and different types of circuitry are designed into one system, that all needs to be simulated, verified and validated before tape-out. Aveek Sarkar, vice president of engineering at Synopsys, talks with Semiconductor Engineering about the intersection of scale complexity and systemic complexity, the rising number of corners, and the reduced margin with which to buffe... » read more

EDA, IP Revenues Soar

By Ed Sperling - 13 Apr, 2021 - Comments: 1

EDA and IP revenues increased 15.4% to $3.032 billion in Q4 2020, according to a just-released report, with huge increases reported in China and India, and a solid double-digit increase in the Americas. EDA/IP revenue from China increased 66.4% in Q4 EDA/IP compared with the same period in 2019, and for the 2020 calendar year it was up 52.3%. India's spending was up 32% for the quarter. And ... » read more

AI Design In Korea

By Kurt Shuler - 08 Oct, 2020 - Comments: 0

Like many in the semiconductor design businesses, Arteris IP is actively working with the Korean chip companies. This shouldn’t be a surprise. If a company is building an SoC of any reasonable size, it needs network-on-chip (NoC) interconnect for optimal QoS (bandwidth and latency regulation and system-level arbitration) and low routing congestion, even in application-centric designs such as ... » read more

The Evolution Of Digital Twins

By Brian Bailey - 03 Aug, 2020 - Comments: 1

Digital twins are starting to make inroads earlier in the chip design flow, allowing design teams to develop more effective models. But they also are adding new challenges in maintaining those models throughout a chip's lifecycle. Until a couple of years ago, few people in the semiconductor industry had even heard the term "digital twin." Then, suddenly, it was everywhere, causing confusion ... » read more

Over-Design, Under-Design Impacts Verification

By Ann Mutschler - 25 Jun, 2020 - Comments: 0

Designing a complex chip today and getting it out the door on schedule and within budget — while including all of the necessary and anticipated features and standards — is forcing engineering teams to make more tradeoffs than in the past, and those tradeoffs now are occurring throughout the flow. In an ideal system design flow, design teams will have done early, pre-design analysis to se... » read more

Best Practices for Deploying ClioSoft SOS7 on AWS

By Cliosoft - 04 Sep, 2019 - Comments: 0

Semiconductor integrated circuits (ICs) are at the center of a number of modern technological innovations. To keep up with the ever-increasing pace of innovation, IC design teams require robust, scalable design management (DM) solutions to enable seamless global collaboration and to increase productivity. This paper outlines the advantages of and best practices for deploying the ClioSoft SOS de... » read more

Safety Critical Design In Automotive

By Ed Sperling - 03 Apr, 2019 - Comments: 0

Shiv Chonnad, hardware engineer at Synopsys, examines how to design chips for safety-critical applications such as automotive and ensure they work as planned and in accordance with ISO 26262 and the various ASIL levels. This includes how to find faults at both a chip and a system level. https://youtu.be/3dL4ZuSe5Ls » read more

EDA, IP Show Strong Growth

By Ed Sperling - 07 Jan, 2019 - Comments: 0

EDA and IP revenue increased 6.7% worldwide in Q3 2018 to $2.44 billion, compared to $2.28 billion in the same period in 2017. The growth was fueled by rising investments in startups in AI and 5G, as well as a stampede of new and existing companies targeting automotive electrification and autonomous vehicles. While startup funding ultimately will run out as these new markets mature and cons... » read more

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Knowledge Centers
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