Tech Talk: 2.5D Issues

By Ed Sperling - 25 Feb, 2016 - Comments: 0

Bill Isaacson, director of ASIC marketing at eSilicon, about how viable this packaging approach is, organic vs. inorganic interposers, where the problems are, thermal coupling, interposer cost, and what will change over the next couple years. » read more

Tech Talk: Mobile Security (Part 2)

By Ed Sperling - 15 Apr, 2015 - Comments: 0

Simon Blake Wilson of Rambus' Cryptography Research Division talks about where security needs to fit into the design flow and where the biggest risks are. To view part one of this video, click here. [youtube vid=_nnniakpP3M] » read more

Tech Talk: 2.5D Stacked Die

By Ed Sperling - 20 Nov, 2013 - Comments: 0

What's the motivation for moving to 2.5D packaging and architectures rather than following Moore's Law? Shafy Eltoukhy, VP of operations and technology development at Open-Silicon, talks with Semiconductor Engineering about adding another dimension in semiconductors. [youtube vid=HwpY9bUNt0w] » read more

The “Last Simple Node” And the Internet of Things

By Brian Fuller - 17 Oct, 2013 - Comments: 0

Power, performance and size are key targets that will enable the expected explosion of the Internet of Things (IoT). Today, most observers see the path to that running directly through 16/14nm finFET and below for the node’s ability to manage power and size and boost integration. Geoff Lees isn’t your average observer. The vice president and general manager of Freescale’s microcon... » read more

Experts At The Table: Does 20nm Break System-Level Design?

By Ed Sperling - 26 Jul, 2012 - Comments: 0

By Ann Steffora Mutschler System-Level Design sat down to discuss design at 20nm with Drew Wingard, chief technology officer at Sonics; Kelvin Low, deputy director of product marketing at GlobalFoundries, Frank Schirrmeister, group director of product marketing for system development in the system and software realization group at Cadence; and Mike Gianfagna, vice president of marketing at At... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.