High-NA EUV Progress And Problems

By Gregory Haley - 22 Aug, 2023 - Comments: 0

High-NA EUV will enable logic scaling for at least the next couple process nodes. It’s complex, expensive, and a feat of optical engineering, but there are a lot of components with mixed progress. Harry Levinson, principal lithographer at HJL Lithography, talks about when this technology will likely show up, what problems still need to be resolved, and what comes next. Related Readin... » read more

AI Process Control Platform Enabling Next Generation Technology

By Tignis - 16 Aug, 2023 - Comments: 0

PAICe Monitor delivers AI and machine learning-enabled analytics for all stages of the semiconductor fabrication process lifecycle — from process development and ramp readiness, to high volume production. Leveraging Tignis’ Digital Twin Query Language, PAICe Monitor enables process engineers to transform in-product fault diagnoses into continuous real-time monitoring—greatly improving ... » read more

Enhancing Punch MLF Packaging with Edge Protection Technology

By Amkor - 14 Jun, 2023 - Comments: 0

Quad Flat No-Lead (QFN) semiconductor packaging provides a small form factor as well as good electrical and thermal performance for low cost. Add demonstrated long term reliability to its benefits and it is easy to see why it has been a preferred automotive package for many years. QFNs are offered in saw and punch formats with punch being a well-defined and used solution in the automotive marke... » read more

Using Advanced Analytics To Meet ESG Goals

By Mike McIntyre - 06 Jun, 2023 - Comments: 0

With the continued advancement of environmental, social and governance goals, corporations are increasingly focused on reducing their carbon footprints. To accomplish this, these companies are being asked to operate their businesses more efficiently than ever before, whether the matter is reducing waste, water usage or power consumption. This is true for the semiconductor industry as well. A... » read more

NIST Releases “Vision And Strategy for the National Semiconductor Technology Center”

By Technical Paper Link - 05 May, 2023 - Comments: 0

A paper titled "A Vision and Strategy for the National Semiconductor Technology Center" was published by the U.S. Department of Commerce’s National Institute of Standards and Technology (NIST). The paper describes how the NSTC (National Semiconductor Technology Center) will develop and safeguard chips and technologies of the future. “The NSTC will be an ambitious public-private consortiu... » read more

How Curvilinear Mask Writing Affects Chip Design

By Ed Sperling - 12 Apr, 2023 - Comments: 0

As chips become more complex and features continue to shrink, it becomes more difficult to print shapes on photomasks. The ability to print curvilinear masks changes that equation, but not all of the pieces in the flow are automated today. Aki Fujimura, CEO of D2S, talks about what has to change, what will the impact be on design rules, and why using curvilinear shapes can shrink the manufactur... » read more

Deep Learning (DL) Applications In Photomask To Wafer Semiconductor Manufacturing

By eBeam Initiative - 15 Mar, 2023 - Comments: 0

Published by the eBeam Initiative Member Companies (February 2023), this list of artificial intelligence (AI) systems used by member companies in their semiconductor manufacturing products shows progress. New examples of systems using AI include: image processing and parameter tuning in lithography tool mask metrology system B-SPline Control Point generation tool sem... » read more

Virtual Process Game To Benchmark Performance of Humans And Computers For Design Of A Semiconductor Fabrication Process

By Technical Paper Link - 09 Mar, 2023 - Comments: 0

A new technical paper titled "Human–machine collaboration for improving semiconductor process development" was published by researchers at Lam Research. Abstract: "One of the bottlenecks to building semiconductor chips is the increasing cost required to develop chemical plasma processes that form the transistors and memory storage cells These processes are still developed manually using h... » read more

New Wafer-Like And Reticle-Like Sensors Deliver Fast, Easy Measurements Inside The Process Chamber

By CyberOptics - 07 Mar, 2023 - Comments: 0

Setup and maintenance operations for semiconductor manufacturing tools can be tedious, time-consuming, and expensive, incurring both direct costs for personnel and resources and indirect costs for lost tool time during extended commissioning of new tools and requalification of repaired or serviced tools. Wafer-like (and reticle-like) sensors (WaferSense® from CyberOptics) provide fast, easy ac... » read more

Week In Review: Semiconductor Manufacturing, Test

By Gregory Haley - 03 Mar, 2023 - Comments: 0

Semiconductor Research Corporation (SRC) released an interim roadmap for Microelectronic and Advanced Packaging Technologies (MPAT) that targets 10- to 15-year goals for 3D integration and multi-chiplet packaging. The roadmap is open for comments. Participants in the MPAT include AMD, IBM, Intel, Texas Instruments, Purdue University, SUNY Binghamton and the Georgia Institute of Technology. It i... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: semiconductor manufacturing